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Difference between revisions of "loongson/godson 2/2g"
< loongson‎ | godson 2

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| frequency 2        =  
 
| frequency 2        =  
 
| frequency N        =  
 
| frequency N        =  
−
| bus type            = <!-- (Property::bus type) -->
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| bus type            = HyperTransport 1.0
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| bus speed          = <!-- (Property::bus speed) -->
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| bus speed          = 400 MHz
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| bus rate            = <!-- (Property::bus rate) -->
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| bus rate            =  
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| bus links          = <!-- ?x bus rate -->
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| bus links          =  
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| clock multiplier    =
+
| clock multiplier    = 2.5
  
 
| isa family          = MIPS
 
| isa family          = MIPS
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}}
 
}}
 
'''Godson-2G''' is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late-[[2010]], the Godson-2G operates at up to 1 GHz consuming up to 4 W. This chip was manufactured on [[STMicroelectronics]]' [[65 nm process]].
 
'''Godson-2G''' is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late-[[2010]], the Godson-2G operates at up to 1 GHz consuming up to 4 W. This chip was manufactured on [[STMicroelectronics]]' [[65 nm process]].
 +
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This specific models incorporates a considerably larger [[2nd level cache]] compared to the rest of the {{\\\|Godson 2}} family along with an extended number of additional interfaces in a relatively large package.
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== Cache ==
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{{main|loongson/microarchitectures/GS464#Memory_Hierarchy|l1=GS464 § Cache}}
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{{cache size
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|l1 cache=128 KiB
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|l1i cache=64 KiB
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|l1i break=1x64 KiB
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|l1i desc=4-way set associative
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|l1d cache=64 KiB
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|l1d break=1x64 KiB
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|l1d desc=4-way set associative
 +
|l1d policy=
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|l2 cache=1 MiB
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|l2 break=1x1 MiB
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|l2 desc=4-way set associative
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|l2 policy=
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR3-800
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|ecc=Yes
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|max mem=4 GiB
 +
|controllers=1
 +
|channels=1
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|max bandwidth=11.92 GiB/s
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|bandwidth schan=11.92 GiB/s
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}}
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== Expansions ==
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This chip has integrated [[HyperTransport]] 1.0 operating at 400 MHz.
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{{expansions
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|pci width  = 32 bit
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|pci clock = 66 MHz
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|pcix width = 32 bit
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|pcix clock = 133 MHz
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|lpc = Yes
 +
}}
  
 
== Die Shot ==
 
== Die Shot ==
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== References ==
 
== References ==
 
* Zhao, Ji-Ye, et al. "Physical Design Methodology for Godson-2G Microprocessor." Journal of Computer Science and Technology 25.2 (2010): 225-231.
 
* Zhao, Ji-Ye, et al. "Physical Design Methodology for Godson-2G Microprocessor." Journal of Computer Science and Technology 25.2 (2010): 225-231.
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* Weiwu Hu, Yunji Chen, "GS464V: A High-Performance Low-Power XPU with 512-Bit Vector Extension", HotChips 22 (2010).

Revision as of 01:14, 19 March 2017

Template:mpu Godson-2G is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in late-2010, the Godson-2G operates at up to 1 GHz consuming up to 4 W. This chip was manufactured on STMicroelectronics' 65 nm process.

This specific models incorporates a considerably larger 2nd level cache compared to the rest of the Godson 2 family along with an extended number of additional interfaces in a relatively large package.

Cache

Main article: GS464 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB4-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Max Mem4 GiB
Controllers1
Channels1
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Expansions

This chip has integrated HyperTransport 1.0 operating at 400 MHz.

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI
Width32 bit
Clock66 MHz
PCI-X
Width32 bit
Clock133 MHz


Die Shot

godson-2g die shot.png

References

  • Zhao, Ji-Ye, et al. "Physical Design Methodology for Godson-2G Microprocessor." Journal of Computer Science and Technology 25.2 (2010): 225-231.
  • Weiwu Hu, Yunji Chen, "GS464V: A High-Performance Low-Power XPU with 512-Bit Vector Extension", HotChips 22 (2010).
Retrieved from "https://en.wikichip.org/w/index.php?title=loongson/godson_2/2g&oldid=39851"
Facts about "Godson-2G - Loongson"
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has ecc memory supporttrue +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description4-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
supported memory typeDDR3-800 +