From WikiChip
Difference between revisions of "loongson/godson 2/2h"
< loongson‎ | godson 2

Line 23: Line 23:
 
| frequency 2        =  
 
| frequency 2        =  
 
| frequency N        =  
 
| frequency N        =  
−
| bus type            = <!-- (Property::bus type) -->
+
| bus type            = HyperTransport 1.03
−
| bus speed          = <!-- (Property::bus speed) -->
+
| bus speed          = 800 MHz
−
| bus rate            = <!-- (Property::bus rate) -->
+
| bus rate            =  
−
| bus links          = <!-- ?x bus rate -->
+
| bus links          =  
−
| clock multiplier    =
+
| clock multiplier    =  
  
 
| isa family          = MIPS
 
| isa family          = MIPS
 
| isa                = MIPS64
 
| isa                = MIPS64
−
| microarch          = GS464
+
| microarch          = GS464V
 
| platform            =  
 
| platform            =  
 
| chipset            =  
 
| chipset            =  
−
| core name          = GS464
+
| core name          = GS464V
 
| core family        =  
 
| core family        =  
 
| core model          =  
 
| core model          =  
 
| core stepping      =  
 
| core stepping      =  
 
| process            = 65 nm
 
| process            = 65 nm
−
| transistors        =  
+
| transistors        = 152,000,000
 
| technology          = CMOS
 
| technology          = CMOS
−
| die area            =  
+
| die area            = 117 mm²
 
| die width          =  
 
| die width          =  
 
| die length          =  
 
| die length          =  
Line 78: Line 78:
 
| tambient max        =  
 
| tambient max        =  
  
−
| packaging          = <!-- put Yes if packaging info is added -->
+
| packaging          = Yes
−
| package 0          =  
+
| package 0          = FCBGA-741
−
| package 0 type      =  
+
| package 0 type      = FCBGA
−
| package 0 pins      =  
+
| package 0 pins      = 741
 
| package 0 pitch    =  
 
| package 0 pitch    =  
−
| package 0 width    =  
+
| package 0 width    = 31 mm
−
| package 0 length    =  
+
| package 0 length    = 31 mm
 
| package 0 height    =  
 
| package 0 height    =  
−
| socket 0            =  
+
| socket 0            = BGA-741
−
| socket 0 type      =  
+
| socket 0 type      = BGA
 
}}
 
}}
 
'''Godson-2H''' is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late-[[2010]], the Godson-2H operates at up to 1 GHz consuming 5 W. This chip was manufactured on [[STMicroelectronics]]' [[65 nm process]].
 
'''Godson-2H''' is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late-[[2010]], the Godson-2H operates at up to 1 GHz consuming 5 W. This chip was manufactured on [[STMicroelectronics]]' [[65 nm process]].
 +
 +
The Godson-2H is actually a complete [[system on a chip]] incorporating the [[northbridge]] along with the [[southbridge]] on-die. Additionally the Godson-2H also incorporates a low-power [[Vivante]] {{vivante|GC800}} [[IGP]] operating at 400 MHz.
 +
 +
In addition to a standalone SoC, the Godson-2H can also operate in slave-mode serving as a cooperative [[southbridge]] to the more powerful {{\\\|Godson 3}} multi-core processor family.
 +
 +
== Cache ==
 +
{{main|loongson/microarchitectures/GS464V#Memory_Hierarchy|l1=GS464V § Cache}}
 +
{{cache size
 +
|l1 cache=128 KiB
 +
|l1i cache=64 KiB
 +
|l1i break=1x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=64 KiB
 +
|l1d break=1x64 KiB
 +
|l1d desc=4-way set associative
 +
|l1d policy=
 +
|l2 cache=512 KiB
 +
|l2 break=1x512 KiB
 +
|l2 desc=4-way set associative
 +
|l2 policy=
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3-800
 +
|ecc=Yes
 +
|max mem=4 GiB
 +
|controllers=1
 +
|channels=1
 +
|max bandwidth=11.92 GiB/s
 +
|bandwidth schan=11.92 GiB/s
 +
}}
 +
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = GC800
 +
| device id          =
 +
| designer            = Vivante
 +
| execution units    = 4
 +
| max displays        =
 +
| max memory          =
 +
| frequency          = 400 MHz
 +
| max frequency      =
 +
 +
| output crt          = Yes
 +
| output sdvo        = Yes
 +
| output dsi          =
 +
| output edp          =
 +
| output dp          =
 +
| output hdmi        =
 +
| output vga          = Yes
 +
| output dvi          =
 +
 +
| directx ver        = 11
 +
| opengl ver        = 3.0
 +
| opencl ver        = 1.1
 +
| opengl es ver      = 2.0
 +
| hdmi ver          =
 +
| dp ver            =
 +
| edp ver            =
 +
| max res hdmi      =
 +
| max res hdmi freq  =
 +
| max res dp        =
 +
| max res dp freq    =
 +
| max res edp        =
 +
| max res edp freq  =
 +
| max res vga        =
 +
| max res vga freq  =
 +
}}
 +
 +
== Expansions ==
 +
This chip has integrated [[HyperTransport]] 1.0 operating at 400 MHz.
 +
{{expansions
 +
|pcie revision=2.0
 +
|pcie lanes=4
 +
|pcie config=1x4
 +
|pcie config 2=4x1
 +
|usb revision=2.0
 +
|usb ports=6
 +
|sata revision=2
 +
|sata ports=2
 +
|lpc revision=1.1
 +
|i2c=Yes
 +
|i2c ports=2
 +
|uart ports=1
 +
|jtag=Yes
 +
|gp io=16 lines
 +
}}
 +
== Networking ==
 +
{{network
 +
|mii opts=Yes
 +
|rgmii=Yes
 +
|spi opts=Yes
 +
}}
 +
 +
== References ==
 +
* Xiao, Bin, et al. "Godson-2H: a complex low power SOC in 65nm CMOS." Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on. IEEE, 2012.

Revision as of 06:08, 19 March 2017

Template:mpu Godson-2H is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in late-2010, the Godson-2H operates at up to 1 GHz consuming 5 W. This chip was manufactured on STMicroelectronics' 65 nm process.

The Godson-2H is actually a complete system on a chip incorporating the northbridge along with the southbridge on-die. Additionally the Godson-2H also incorporates a low-power Vivante GC800 IGP operating at 400 MHz.

In addition to a standalone SoC, the Godson-2H can also operate in slave-mode serving as a cooperative southbridge to the more powerful Godson 3 multi-core processor family.

Cache

Main article: GS464V § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB4-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Max Mem4 GiB
Controllers1
Channels1
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUGC800
DesignerVivante
Execution Units4
Frequency400 MHz
0.4 GHz
400,000 KHz
OutputVGA, SDVO, CRT
Standards
DirectX11
OpenGL3.0
OpenCL1.1
OpenGL ES2.0

Expansions

This chip has integrated HyperTransport 1.0 operating at 400 MHz.

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes4
Configs1x4, 4x1
USB
Revision2.0
Ports6
SATA
Revision2
Ports2
LPC
Revision1.1
I²C
Ports2
GP I/O16 lines
JTAGYes

Networking

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes

References

  • Xiao, Bin, et al. "Godson-2H: a complex low power SOC in 65nm CMOS." Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on. IEEE, 2012.
Retrieved from "https://en.wikichip.org/w/index.php?title=loongson/godson_2/2h&oldid=39865"
Facts about "Godson-2H - Loongson"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Godson-2H - Loongson#io +
has ecc memory supporttrue +
integrated gpuGC800 +
integrated gpu base frequency400 MHz (0.4 GHz, 400,000 KHz) +
integrated gpu designerVivante +
integrated gpu execution units4 +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description4-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
max pcie lanes4 +
supported memory typeDDR3-800 +