Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/microarchitectures/gen10"
| Line 16: | Line 16: | ||
}} | }} | ||
'''Gen10''' (''Generation 10'') is the [[microarchitecture]] for [[Intel]]'s [[graphics processing unit]] utilized by {{\\|Cannonlake}}-based microprocessors. Gen10 is the successor to {{\\|Gen9.5}} used by {{\\|Kaby Lake}}. | '''Gen10''' (''Generation 10'') is the [[microarchitecture]] for [[Intel]]'s [[graphics processing unit]] utilized by {{\\|Cannonlake}}-based microprocessors. Gen10 is the successor to {{\\|Gen9.5}} used by {{\\|Kaby Lake}}. | ||
| + | |||
| + | == Codenames == | ||
| + | [[File:iris graphics logo.svg|right|200px]] | ||
| + | Various models support different Graphics Tiers (GT) which provides different levels of performance. Some models also support an additional [[eDRAM]] side cache. | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! Code Name !! Description | ||
| + | |- | ||
| + | | GT1 || Contains 1 slice with 12 execution units. | ||
| + | |- | ||
| + | | GT2 || Contains 1 slice with 24 execution units. | ||
| + | |- | ||
| + | | GT3 || Contains 2 slices with 48 execution units. | ||
| + | |- | ||
| + | | GT3e || Contains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache. | ||
| + | |- | ||
| + | | GT4e || Contains 3 slices with 72 execution units. Has an additional [[eDRAM]] side cache. | ||
| + | |} | ||
| + | |||
| + | == Models == | ||
| + | {{empty section}} | ||
| + | |||
| + | == Hardware Accelerated Video == | ||
| + | {{empty section}} | ||
| + | |||
| + | == Architecture == | ||
| + | |||
| + | === Key changes from {{\\|Gen9.5}} === | ||
| + | {{empty section}} | ||
Revision as of 21:57, 27 January 2017
| Edit Values | |
| Gen10 µarch | |
| General Info | |
| Arch Type | GPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2017 |
| Process | 10 nm |
| Succession | |
Gen10 (Generation 10) is the microarchitecture for Intel's graphics processing unit utilized by Cannonlake-based microprocessors. Gen10 is the successor to Gen9.5 used by Kaby Lake.
Contents
Codenames
Various models support different Graphics Tiers (GT) which provides different levels of performance. Some models also support an additional eDRAM side cache.
| Code Name | Description |
|---|---|
| GT1 | Contains 1 slice with 12 execution units. |
| GT2 | Contains 1 slice with 24 execution units. |
| GT3 | Contains 2 slices with 48 execution units. |
| GT3e | Contains 2 slices with 48 execution units. Has an additional eDRAM side cache. |
| GT4e | Contains 3 slices with 72 execution units. Has an additional eDRAM side cache. |
Models
 |
This section is empty; you can help add the missing info by editing this page. |
Hardware Accelerated Video
| |
This section is empty; you can help add the missing info by editing this page. |
Architecture
Key changes from Gen9.5
| |
This section is empty; you can help add the missing info by editing this page. |
Facts about "Gen10 - Microarchitectures - Intel"
| codename | Gen10 + |
| designer | Intel + |
| first launched | 2017 + |
| full page name | intel/microarchitectures/gen10 + |
| instance of | microarchitecture + |
| manufacturer | Intel + |
| microarchitecture type | GPU + |
| name | Gen10 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |