Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/microarchitectures/cannon lake"
(→Architecture) |
|||
| Line 1: | Line 1: | ||
{{intel title|Cannonlake|arch}} | {{intel title|Cannonlake|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
| + | | atype = CPU | ||
| name = Cannonlake | | name = Cannonlake | ||
| designer = Intel | | designer = Intel | ||
Revision as of 18:20, 21 January 2017
| Edit Values | |
| Cannonlake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2017 |
| Process | 10 nm |
| Cores | |
| Core Names | Cannonlake Y, Cannonlake U |
| Succession | |
Cannonlake (CNL) is a planned microarchitecture by Intel as a successor to Kaby Lake. Cannonlake is expected to be fabricated using a 10 nm process and is set to be introduced in the fourth quarter of 2017. Cannonlake is the "Process" microarchitecture as part of Intel's PAO model.
For desktop and mobile, Cannonlake is expected to be branded as 8th Generation Intel Core i3, Core i5. and Core i7 processors. For server class processors, Intel is expected to brand it as Xeon E3 v7, Xeon E5 v7, and Xeon E7 v7.
Contents
Process Technology
Cannonlake is set to utilize Intel's 10 nm process (P1274).
 |
This section requires expansion; you can help adding the missing info. |
Codenames
| Core | Abbrev | Description | Graphics | Target |
|---|---|---|---|---|
| Cannonlake Y | CNL-Y | Extremely low power | GT2 | 2-in-1s detachable, tablets, and computer sticks |
| Cannonlake U | CNL-U | Ultra-low Power | GT2 | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
Architecture
| |
This section is empty; you can help add the missing info by editing this page. |
Key changes from Kaby Lake
| |
This section is empty; you can help add the missing info by editing this page. |
All Cannonlake Chips
| Cannonlake Chips | |||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Main processor | IGP | Major Feature Diff | |||||||||||||||||||||
| Model | Launched | Price | Family | Platform | Core | C | T | L3$ | L4$ | TDP | Freq | Turbo | Max Mem | Name | Freq | Turbo | TBT | HT | AVX2 | TXT | TSX | vPro | VT-d |
| Uniprocessors | |||||||||||||||||||||||
| No Cannonlake Chips have been released yet. | |||||||||||||||||||||||
| Count: 0 | |||||||||||||||||||||||
See also
- AMD's Zen
Facts about "Cannon Lake - Microarchitectures - Intel"
| codename | Cannonlake + |
| designer | Intel + |
| first launched | 2017 + |
| full page name | intel/microarchitectures/cannon lake + |
| instance of | microarchitecture + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Cannonlake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |