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Difference between revisions of "cavium/octeon plus/cn5734-800bg1217-sp"
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| socket 0 = BGA-1217 | | socket 0 = BGA-1217 | ||
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| + | '''CN5734-800 SP''' is a {{arch|64}} [[hexa-core]] [[MIPS]] storage processor (SP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates six {{cavium|cnMIPS|l=arch}} cores, operates at 800 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], networking, TCP & [[QoS]] acceleration. | ||
Revision as of 23:50, 28 December 2016
Template:mpu CN5734-800 SP is a 64-bit hexa-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates six cnMIPS cores, operates at 800 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.
Facts about "CN5734-800 SP - Cavium"
