From WikiChip
Difference between revisions of "intel/core m/m3-6y30"
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{{mpu | {{mpu | ||
| name = Core M3-6Y30 | | name = Core M3-6Y30 | ||
− | | no image = | + | | no image = |
− | | image = | + | | image = skylake y (front).png |
− | | image size = | + | | image size = 250px |
| caption = | | caption = | ||
| designer = Intel | | designer = Intel | ||
Line 15: | Line 15: | ||
| last order = | | last order = | ||
| last shipment = | | last shipment = | ||
+ | | release price = $281 | ||
| family = Core M3 | | family = Core M3 | ||
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| isa = x86-64 | | isa = x86-64 | ||
| microarch = Skylake | | microarch = Skylake | ||
− | | platform = | + | | platform = Skylake |
| chipset = | | chipset = | ||
| core name = Skylake Y | | core name = Skylake Y | ||
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| core stepping = D1 | | core stepping = D1 | ||
| process = 14 nm | | process = 14 nm | ||
− | | transistors = | + | | transistors = 1,750,000,000 |
| technology = CMOS | | technology = CMOS | ||
− | | die | + | | die area = 98.57 mm² |
+ | | die width = 9.57 mm | ||
+ | | die length = 10.3 mm | ||
| word size = 64 bit | | word size = 64 bit | ||
| core count = 2 | | core count = 2 | ||
| thread count = 4 | | thread count = 4 | ||
| max cpus = 1 | | max cpus = 1 | ||
− | | max memory = 16 | + | | max memory = 16 GiB |
| electrical = Yes | | electrical = Yes | ||
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| ctdp up = 7 W | | ctdp up = 7 W | ||
| ctdp up frequency = 1500 MHz | | ctdp up frequency = 1500 MHz | ||
− | | | + | | tjunc min = 5 °C |
− | | | + | | tjunc max = 100 °C |
− | + | | package module 1 = {{packages/intel/fcbga-1515}} | |
− | | package | ||
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}} | }} | ||
− | + | '''Core M3-6Y30''' is an ultra-low power {{arch|64}} [[dual-core]] [[x86]] microprocessor introduced by [[Intel]] in late 2015. This MPU operates at 900 MHz with a max turbo frequency of 2.2 GHz. This chip, which is manufactured on a [[14 nm process]], is based on the {{intel|Skylake}} microarchitecture. The Core M3-6Y30 incorporates Intel's {{intel|HD Graphics 515}} Gen9 GPU clocked at 300 MHz with turbo frequency of 850 MHz. | |
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
− | {{cache | + | {{cache size |
+ | |l1 cache=128 KiB | ||
|l1i cache=64 KiB | |l1i cache=64 KiB | ||
|l1i break=2x32 KiB | |l1i break=2x32 KiB | ||
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
− | |||
|l1d cache=64 KiB | |l1d cache=64 KiB | ||
|l1d break=2x32 KiB | |l1d break=2x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
− | |l1d | + | |l1d policy=write-back |
|l2 cache=512 KiB | |l2 cache=512 KiB | ||
|l2 break=2x256 KiB | |l2 break=2x256 KiB | ||
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
− | |l2 | + | |l2 policy=write-back |
|l3 cache=4 MiB | |l3 cache=4 MiB | ||
|l3 break=2x2 MiB | |l3 break=2x2 MiB | ||
− | |l3 | + | |l3 policy=write-back |
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=LPDDR3-1866 | ||
+ | |ecc=No | ||
+ | |max mem=16 GiB | ||
+ | |controllers=1 | ||
+ | |channels=2 | ||
+ | |max bandwidth=27.81 GiB/s | ||
+ | |bandwidth schan=13.91 GiB/s | ||
+ | |bandwidth dchan=27.81 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 10 | ||
+ | | pcie config = 1x4 | ||
+ | | pcie config 2 = 2x2 | ||
+ | | pcie config 3 = 1x2+2x1 | ||
+ | | pcie config 4 = 4x1 | ||
}} | }} | ||
== Graphics == | == Graphics == | ||
− | {{integrated | + | {{integrated graphics |
− | | gpu = | + | | gpu = HD Graphics 515 |
| device id = 0x191E | | device id = 0x191E | ||
+ | | designer = Intel | ||
| execution units = 24 | | execution units = 24 | ||
− | | displays | + | | max displays = 3 |
+ | | max memory = 16 GiB | ||
| frequency = 300 MHz | | frequency = 300 MHz | ||
| max frequency = 850 MHz | | max frequency = 850 MHz | ||
− | |||
| output crt = | | output crt = | ||
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| output dvi = Yes | | output dvi = Yes | ||
− | | directx ver | + | | directx ver = 12 |
− | | opengl ver | + | | opengl ver = 4.4 |
− | | opencl ver | + | | opencl ver = 2.0 |
− | + | | hdmi ver = 1.4a | |
− | | hdmi ver | + | | dp ver = 1.2 |
− | | | + | | edp ver = 1.3 |
− | + | | max res hdmi = 4096x2304 | |
− | + | | max res hdmi freq = 24 Hz | |
− | + | | max res dp = 3840x2160 | |
− | | edp ver | + | | max res dp freq = 60 Hz |
− | + | | max res edp = 3840x2160 | |
− | | max res hdmi | + | | max res edp freq = 60 Hz |
− | | max res hdmi freq | + | | max res vga = |
− | | max res | + | | max res vga freq = |
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− | | max res dp freq | ||
− | | max res | ||
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− | | max res edp freq | ||
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− | | max res vga | ||
− | | max res vga freq | ||
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− | == | + | | features = Yes |
− | + | | intel quick sync = Yes | |
− | | | + | | intel intru 3d = Yes |
− | | | + | | intel insider = |
− | | | + | | intel widi = |
− | | | + | | intel fdi = |
− | | | + | | intel clear video = Yes |
− | | | + | | intel clear video hd = Yes |
}} | }} | ||
+ | {{skylake hardware accelerated video table|col=1}} | ||
== Features == | == Features == |
Revision as of 21:16, 3 June 2017
Template:mpu Core M3-6Y30 is an ultra-low power 64-bit dual-core x86 microprocessor introduced by Intel in late 2015. This MPU operates at 900 MHz with a max turbo frequency of 2.2 GHz. This chip, which is manufactured on a 14 nm process, is based on the Skylake microarchitecture. The Core M3-6Y30 incorporates Intel's HD Graphics 515 Gen9 GPU clocked at 300 MHz with turbo frequency of 850 MHz.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
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Integrated Graphics Information
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[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
---|---|---|---|---|---|---|---|
Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
VP9 | ✘ | 0 | Unified | 2160p (4K) |
Features
Drivers
Facts about "Core m3-6Y30 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core m3-6Y30 - Intel#io + |
base frequency | 900 MHz (0.9 GHz, 900,000 kHz) + |
bus type | DMI 3.0 + |
clock multiplier | 9 + |
core count | 2 + |
core family | 6 + |
core model | 78 + |
core name | Skylake Y + |
core stepping | D1 + |
designer | Intel + |
device id | 0x191E + |
die area | 98.57 mm² (0.153 in², 0.986 cm², 98,570,000 µm²) + |
die count | 2 + |
die length | 10.3 mm (1.03 cm, 0.406 in, 10,300 µm) + |
die width | 9.57 mm (0.957 cm, 0.377 in, 9,570 µm) + |
drivers url | https://downloadcenter.intel.com/product/94027 + |
family | Core m3 + |
first announced | September 1, 2015 + |
first launched | September 27, 2015 + |
full page name | intel/core m/m3-6y30 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel my wifi technology support | true + |
has intel secure key technology | true + |
has intel smart response technology support | true + |
has intel supervisor mode execution protection | true + |
has intel turbo boost technology 2 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | HD Graphics 515 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 850 MHz (0.85 GHz, 850,000 KHz) + |
integrated gpu max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB) + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
ldate | September 27, 2015 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Mobile + |
max cpu count | 1 + |
max junction temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) + |
max memory bandwidth | 27.81 GiB/s (28,477.44 MiB/s, 29.861 GB/s, 29,860.76 MB/s, 0.0272 TiB/s, 0.0299 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 10 + |
microarchitecture | Skylake + |
min junction temperature | 278.15 K (5 °C, 41 °F, 500.67 °R) + |
model number | m3-6Y30 + |
name | Core m3-6Y30 + |
package | FCBGA-1515 + |
part number | HE8066201930521 + |
platform | Skylake + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 281.00 (€ 252.90, £ 227.61, ¥ 29,035.73) + |
s-spec | SR2EN + |
sdp | 3 W (3,000 mW, 0.00402 hp, 0.003 kW) + |
series | m-6Y + |
smp max ways | 1 + |
supported memory type | LPDDR3-1866 + and DDR3L-1600 + |
tdp | 4.5 W (4,500 mW, 0.00603 hp, 0.0045 kW) + |
tdp down | 3.8 W (3,800 mW, 0.0051 hp, 0.0038 kW) + |
tdp down frequency | 600 MHz (0.6 GHz, 600,000 kHz) + |
tdp up | 7 W (7,000 mW, 0.00939 hp, 0.007 kW) + |
tdp up frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) + |
technology | CMOS + |
thread count | 4 + |
transistor count | 1,750,000,000 + |
turbo frequency (1 core) | 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
turbo frequency (2 cores) | 2,000 MHz (2 GHz, 2,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |