Difference between revisions of "intel/xeon e3/e3-1220 v6"

Revision as of 21:35, 11 January 2017

Template:mpu The Xeon E3-1220 v6 is a 64-bit quad-core x86 microprocessor set to be introduced by Intel in late 2016 or early 2017. Operating at 3 GHz, this MPU has a TDP of 74 W. This processor is a Kaby Lake-based chip and is manufactured on a Intel's 14 nm process.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative	write-back
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative	write-back

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		4x256 KiB	4-way set associative	write-back

L3$

8 MiB

8,192 KiB
8,388,608 B
0.00781 GiB

		4x2 MiB	16-way set associative	write-back

@@ Line 78: / Line 78: @@
 == Cache ==
-{{main|intel/microarchitectures/kaby lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
+{{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
-{{cache info
+{{cache size
+|l1 cache=256 KiB
 |l1i cache=128 KiB
 |l1i break=4x32 KiB
 |l1i desc=8-way set associative
-|l1i extra=(per core, write-back)
+|l1i policy=write-back
 |l1d cache=128 KiB
 |l1d break=4x32 KiB
 |l1d desc=8-way set associative
-|l1d extra=(per core, write-back)
+|l1d policy=write-back
 |l2 cache=1 MiB
 |l2 break=4x256 KiB
 |l2 desc=4-way set associative
-|l2 extra=(per core, write-back)
+|l2 policy=write-back
 |l3 cache=8 MiB
-|l3 desc=shared
+|l3 break=4x2 MiB
+|l3 desc=16-way set associative
+|l3 policy=write-back
 }}

l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	4-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description	shared +
l3$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +

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Revision as of 21:35, 11 January 2017

Cache