Difference between revisions of "intel/xeon e3/e3-1220 v6"

Revision as of 21:35, 11 January 2017

Template:mpu The Xeon E3-1220 v6 is a 64-bit quad-core x86 microprocessor set to be introduced by Intel in late 2016 or early 2017. Operating at 3 GHz, this MPU has a TDP of 74 W. This processor is a Kaby Lake-based chip and is manufactured on a Intel's 14 nm process.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative	write-back
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative	write-back

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		4x256 KiB	4-way set associative	write-back

L3$

8 MiB

8,192 KiB
8,388,608 B
0.00781 GiB

		4x2 MiB	16-way set associative	write-back

@@ Line 78: / Line 78: @@
 == Cache ==
-{{main|intel/microarchitectures/kaby lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
+{{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
-{{cache info
+{{cache size
+|l1 cache=256 KiB
 |l1i cache=128 KiB
 |l1i break=4x32 KiB
 |l1i desc=8-way set associative
-|l1i extra=(per core, write-back)
+|l1i policy=write-back
 |l1d cache=128 KiB
 |l1d break=4x32 KiB
 |l1d desc=8-way set associative
-|l1d extra=(per core, write-back)
+|l1d policy=write-back
 |l2 cache=1 MiB
 |l2 break=4x256 KiB
 |l2 desc=4-way set associative
-|l2 extra=(per core, write-back)
+|l2 policy=write-back
 |l3 cache=8 MiB
-|l3 desc=shared
+|l3 break=4x2 MiB
+|l3 desc=16-way set associative
+|l3 policy=write-back
 }}

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon E3-1220 v6 - Intel#package +, Xeon E3-1220 v6 - Intel#io + and Xeon E3-1220 v6 - Intel +
base frequency	3,000 MHz (3 GHz, 3,000,000 kHz) +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Sunrise Point + and Union Point +
clock multiplier	30 +
core count	4 +
core family	6 +
core model	158 +
core name	Kaby Lake DT +
core stepping	B0 +
core voltage (max)	1.52 V (15.2 dV, 152 cV, 1,520 mV) +
core voltage (min)	0.55 V (5.5 dV, 55 cV, 550 mV) +
designer	Intel +
family	Xeon E3 +
first announced	March 28, 2017 +
first launched	March 28, 2017 +
full page name	intel/xeon e3/e3-1220 v6 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology + and OS Guard +
has intel enhanced speedstep technology	true +
has intel secure key technology	true +
has intel speed shift technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	4-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description	16-way set associative +
l3$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldate	March 28, 2017 +
manufacturer	Intel +
market segment	Workstation + and Server +
max cpu count	1 +
max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth	35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels	2 +
max pcie lanes	16 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Kaby Lake +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	E3-1220 v6 +
name	Xeon E3-1220 v6 +
package	FCLGA-1151 +
part number	CM8067702870812 + and BX80677E31220V6 +
platform	Greenlow +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 193.00 (€ 173.70, £ 156.33, ¥ 19,942.69) +
s-spec	SR329 +
series	E3-1200 v6 +
smp max ways	1 +
socket	LGA-1151 +
supported memory type	DDR3L-1866 + and DDR4-2400 +
tdp	72 W (72,000 mW, 0.0966 hp, 0.072 kW) +
technology	CMOS +
thread count	4 +
turbo frequency (1 core)	3,500 MHz (3.5 GHz, 3,500,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +
x86/has software guard extensions	true +

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Revision as of 21:35, 11 January 2017

Cache