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Difference between revisions of "mediatek/helio/mt6795t"
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| temp max = 80 °C | | temp max = 80 °C | ||
| tjunc min = | | tjunc min = | ||
| − | | tjunc max = 125 °C | + | | tjunc max = 125 °C |
| tcase min = | | tcase min = | ||
| tcase max = | | tcase max = | ||
| − | | tstorage min = | + | | tstorage min = 0 °C |
| − | | tstorage max = | + | | tstorage max = 125 °C |
| tambient min = | | tambient min = | ||
| tambient max = | | tambient max = | ||
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| package 0 height = 0.78 mm | | package 0 height = 0.78 mm | ||
}} | }} | ||
| − | '''Helio X10''' ('''MT6795T''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in | + | '''Helio X10''' ('''MT6795T''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in early-[[2014]]. This SoC, which incorporates eight {{armh|Cortex-A53}} cores and is manufactured on TSMC's [[28 nm process]], operates at up to 2.2 GHz and supports dual-channel LPDDR3-933. This chip incorporates the {{imgtec|PowerVR G6200}} [[IGP]] operating at 700 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 4. |
| − | This SoC is made of 2 clusters of 4-core each ({{armh|Cortex-A53}}) linked together via a {{armh|CCI-400}}, a {{armh|NEON}} engine, and {{armh|Cortex-R4}} core for the MCU subsystem. | + | This SoC is made of 2 clusters of 4-core each ({{armh|Cortex-A53}}) linked together via a {{armh|CCI-400}}, a {{armh|NEON}} engine, and {{armh|Cortex-R4}} core for the second MCU subsystem. |
| + | |||
| + | == Cache == | ||
| + | {{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A53 § Cache}} | ||
| + | {{cache size | ||
| + | |l1 cache = 512 KiB | ||
| + | |l1i cache=256 KiB | ||
| + | |l1i break=8x32 KiB | ||
| + | |l1i desc=2-way set associative | ||
| + | |l1d cache=256 KiB | ||
| + | |l1d break=8x32 KiB | ||
| + | |l1d desc=4-way set associative | ||
| + | |l2 cache=2 MiB | ||
| + | |l2 break=2x1 MiB | ||
| + | |l2 desc=16-way set associative | ||
| + | }} | ||
Revision as of 02:38, 3 December 2016
Template:mpu Helio X10 (MT6795T) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and introduced in early-2014. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 28 nm process, operates at up to 2.2 GHz and supports dual-channel LPDDR3-933. This chip incorporates the PowerVR G6200 IGP operating at 700 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 4.
This SoC is made of 2 clusters of 4-core each (Cortex-A53) linked together via a CCI-400, a NEON engine, and Cortex-R4 core for the second MCU subsystem.
Cache
- Main article: Cortex-A53 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Helio X10 T (MT6795T) - MediaTek"
| l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |