From WikiChip
Difference between revisions of "intel/core i7ee/i7-940xm"
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== Features == | == Features == | ||
− | {{ | + | {{x86 features |
− | | | + | |real=Yes |
− | | | + | |protected=Yes |
− | | | + | |smm=Yes |
− | | | + | |fpu=Yes |
− | | | + | |x8616=Yes |
− | | | + | |x8632=Yes |
− | | | + | |x8664=Yes |
− | | | + | |nx=Yes |
− | | | + | |3dnow=No |
− | | | + | |e3dnow=No |
− | | | + | |mmx=Yes |
− | | | + | |emmx=Yes |
− | | sse | + | |sse=Yes |
− | | sse2 | + | |sse2=Yes |
− | | sse3 | + | |sse3=Yes |
− | | ssse3 | + | |ssse3=Yes |
− | | | + | |sse41=Yes |
− | | | + | |sse42=Yes |
− | | | + | |sse4a=No |
− | | | + | |avx=No |
− | | | + | |avx2=No |
− | | | + | |avx512=No |
− | | | + | |abm=No |
− | | bmi1 | + | |tbm=No |
− | | bmi2 | + | |bmi1=No |
− | | f16c | + | |bmi2=No |
− | | | + | |fma3=No |
− | | | + | |fma4=No |
− | | eist | + | |aes=No |
− | | | + | |rdrand=No |
− | | | + | |sha=No |
+ | |xop=No | ||
+ | |adx=No | ||
+ | |clmul=No | ||
+ | |f16c=No | ||
+ | |tbt1=Yes | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |flex=No | ||
+ | |isrt=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=No | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdv=No | ||
+ | |rvi=No | ||
}} | }} | ||
== See also == | == See also == | ||
* {{intel|Core i7EE|Core i7 Extreme Edition}} | * {{intel|Core i7EE|Core i7 Extreme Edition}} |
Revision as of 00:04, 27 November 2016
Template:mpu The Core i7-940XM Extreme Edition is a 64-bit quad-core microprocessor introduced by Intel in early 2010 for the mobile market. The Core i7-940XM EE, which operated at 2.13 GHz with turbo frequency of up to 3.33 GHz for a single core was Intel's flagship mobile processor for the Nehalem microarchitecture. The 940XM is identical to the i7-920XM but with a faster clock. The chip is manufactured in 45 nm process. The i7-940XM supports 8GB of memory and has a thermal design power of 55 W.
Cache
- Main article: Nehalem § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Graphics
This MPU has no integrated graphics processing unit.
Expansions
Expansion Options
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Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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See also
Facts about "Core i7-940XM Extreme Edition - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i7-940XM Extreme Edition - Intel#io + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Hyper-Threading Technology +, Turbo Boost Technology 1.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 1 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
max memory bandwidth | 19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | DDR3-1333 + |