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Difference between revisions of "intel/core i7ee/i7-920xm"
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== Memory controller ==
 
== Memory controller ==
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{{integrated memory controller
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{{memory controller
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| type               = DDR3-1066
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|type=DDR3-1333
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| type 2            = DDR3-1333
+
|controllers=1
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| controllers       = 1
+
|channels=2
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| channels           = 2
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|max bandwidth=19.87 GiB/s
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| ecc support        = No
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|max memory=8 GiB
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| max bandwidth      = 21 GB/s
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|bandwidth schan=9.93 GiB/s
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| bandwidth schan   =  
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|bandwidth dchan=19.87 GiB/s
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| bandwidth dchan   =  
 
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| max memory        = 8 GB
 
 
}}
 
}}
  

Revision as of 22:14, 26 November 2016

Template:mpu Core i7-920XM Extreme Edition is a 64-bit quad-core microprocessor introduced by Intel in late 2009 for the mobile market. The Core i7-920XM EE, which operated at 2 GHz with turbo frequency of up to 3.2 GHz for a single core was Intel's flagship mobile processor for the Nehalem microarchitecture. The chip is manufactured in 45 nm process. The i7-920XM supports 8GB of memory and has a thermal design power of 55 W.

Cache

Main article: Nehalem § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB4-way set associativewrite-back
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB8-way set associativewrite-back
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1333
Controllers1
Channels2
Max Bandwidth19.87 GiB/s
20,346.88 MiB/s
21.335 GB/s
21,335.25 MB/s
0.0194 TiB/s
0.0213 TB/s
Bandwidth
Single 9.93 GiB/s
Double 19.87 GiB/s

Graphics

This MPU has no integrated graphics processing unit.

Expansions

Template:mpu expansions

Features

Template:mpu features

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i7ee/i7-920xm&oldid=29180"
Facts about "Core i7-920XM Extreme Edition - Intel"
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has ecc memory supportfalse +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description16-way set associative +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
max memory bandwidth19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) +
max memory channels2 +
supported memory typeDDR3-1333 +