Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i7/i7-840qm"
| Line 101: | Line 101: | ||
|l3 break=4x2 MiB | |l3 break=4x2 MiB | ||
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
| − | |l3 policy=write- | + | |l3 policy=write- |
| + | |||
| + | == Memory controller == | ||
| + | {{memory controller | ||
| + | |type=DDR3-1333 | ||
| + | |controllers=1 | ||
| + | |channels=2 | ||
| + | |ecc=no | ||
| + | |max bandwidth=19.87 GiB/s | ||
| + | |max memory=8 GiB | ||
| + | |bandwidth schan=9.93 GiB/s | ||
| + | |bandwidth dchan=19.87 GiB/s | ||
| + | |pae=36 bit | ||
}} | }} | ||
Revision as of 22:17, 26 November 2016
Template:mpu Core i7-820QM is a 64-bit x86 quad-core mobile performance microprocessor introduced by Intel late 2010. The processor has a base frequency of 1.86 GHz with a turbo frequency of 3.20 GHz and a TDP of 45 W. This MPU is based on the Clarksfield core (Nehalem) and is manufactured on Intel's 45 nm process.
Cache
- Main article: Nehalem § Cache
{{cache size |l1 cache=256 KiB |l1i cache=128 KiB |l1i break=4x32 KiB |l1i desc=4-way set associative |l1i policy=write-back |l1d cache=128 KiB |l1d break=4x32 KiB |l1d desc=8-way set associative |l1d policy=write-back |l2 cache=1 MiB |l2 break=4x256 KiB |l2 desc=8-way set associative |l2 policy=write-back |l3 cache=8 MiB |l3 break=4x2 MiB |l3 desc=16-way set associative |l3 policy=write-
Memory controller
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Integrated Memory Controller
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Facts about "Core i7-840QM - Intel"
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |