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Difference between revisions of "amd/athlon mp/amsn2000dkt3c"
< amd‎ | athlon mp

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| tstorage max        = 100 °C
 
| tstorage max        = 100 °C
  
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| packaging          = Yes
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|package module 1={{packages/amd/pga-453}}
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| package 0          = OPGA-453
 
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| package 0 type      = OPGA
 
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| package 0 pins      = 453
 
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| package 0 pitch    = 1.27 mm
 
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| package 0 width    = 49.53 mm
 
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| package 0 length    = 49.53 mm
 
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| package 0 height    = 1.942
 
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| socket 0            = Socket A
 
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| socket 0 type      = PGA-462
 
 
}}
 
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The '''Athlon MP 2000+''' (OPN ''AMSN2000DKT3C'') based on the {{amd|Thoroughbred|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2002]] for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12.5 multiplier), was manufactured on a newer [[130 nm]] copper processor technology in Fab 30 in Dresden, Germany.
 
The '''Athlon MP 2000+''' (OPN ''AMSN2000DKT3C'') based on the {{amd|Thoroughbred|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2002]] for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12.5 multiplier), was manufactured on a newer [[130 nm]] copper processor technology in Fab 30 in Dresden, Germany.

Revision as of 00:20, 23 June 2017

Template:mpu The Athlon MP 2000+ (OPN AMSN2000DKT3C) based on the Thoroughbred core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2002 for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12.5 multiplier), was manufactured on a newer 130 nm copper processor technology in Fab 30 in Dresden, Germany.

Cache

Main article: K7 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB2-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB2-way set associative 
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB16-way set associative 

Graphics

This MPU has no integrated graphics processing unit.

Features

[Edit/Modify Supported Features]

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Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
3DNow!3DNow! Extension
E3DNow!Extended 3DNow! Extension
SSEStreaming SIMD Extensions
x86-1616-bit x86
x86-3232-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
SmartMPSmartMP Technology
  • Advanced Configuration and Power Interface
    • Halt State
    • Stop Grant State

Documents

Datasheets

Others

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/athlon_mp/amsn2000dkt3c&oldid=46379"
Facts about "Athlon MP 2000+ - AMD"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Athlon MP 2000+ - AMD#package +
base frequency1,667 MHz (1.667 GHz, 1,667,000 kHz) +
bus rate266 MT/s (0.266 GT/s, 266,000 kT/s) +
bus speed133 MHz (0.133 GHz, 133,000 kHz) +
bus typeFSB +
chipsetAMD-760MP +
clock multiplier12.5 +
core count1 +
core family6 +
core model8 +
core nameThoroughbred +
core stepping0 + and 1 +
core voltage1.65 V (16.5 dV, 165 cV, 1,650 mV) +
cpuid680 + and 681 +
designerAMD +
die area85 mm² (0.132 in², 0.85 cm², 85,000,000 µm²) +
familyAthlon MP +
first announcedAugust 27, 2002 +
first launchedAugust 27, 2002 +
full page nameamd/athlon mp/amsn2000dkt3c +
has amd smartmp technologytrue +
has featureACPI +, Halt State +, SmartMP Technology + and Stop Grant State +
has locked clock multipliertrue +
has multiprocessing supporttrue +
instance ofmicroprocessor +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldateAugust 27, 2002 +
manufacturerAMD +
market segmentServer +
max case temperature363.15 K (90 °C, 194 °F, 653.67 °R) +
max cpu count2 +
max junction temperature363.15 K (90 °C, 194 °F, 653.67 °R) +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max storage temperature373.15 K (100 °C, 212 °F, 671.67 °R) +
microarchitectureK7 +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
model numberAthlon MP 2000+ +
nameAMD Athlon MP 2000+ +
packageOPGA-453 +
part numberAMSN2000DKT3C +
platformAthlon MP +
process130 nm (0.13 μm, 1.3e-4 mm) +
smp max ways2 +
technologyCMOS +
thread count1 +
transistor count37,200,000 +
word size32 bit (4 octets, 8 nibbles) +