From WikiChip
Difference between revisions of "intel/celeron/3755u"
< intel‎ | celeron

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| pcie lanes        = 12
 
| pcie lanes        = 12
 
| pcie config        = 4x1+2x4
 
| pcie config        = 4x1+2x4
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}}
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== Features ==
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{{mpu features
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| em64t      = Yes
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| nx          = Yes
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| txt        =
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| tsx        =
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| vpro        =
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| ht          =
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| tbt1        =
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| tbt2        =
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| tbmt3      =
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| bpt        =
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| vt-x        = Yes
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| vt-d        = Yes
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| ept        = Yes
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| mmx        = Yes
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| sse        = Yes
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| sse2        = Yes
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| sse3        = Yes
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| ssse3      = Yes
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| sse4.1      = Yes
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| sse4.2      = Yes
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| aes        =
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| pclmul      =
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| avx        =
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| avx2        =
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| bmi        =
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| bmi1        =
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| bmi2        =
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| f16c        =
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| fma3        =
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| mpx        =
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| sgx        =
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| eist        = Yes
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| secure key  = Yes
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| os guard    = Yes
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| intel at    =
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| intel ipt  =
 
}}
 
}}

Revision as of 12:28, 13 November 2016

Template:mpu Celeron 3755U is a 64-bit dual-core x86 mobile microprocessor introduced by Intel in early 2015. Operating at 1.7 GHz with a TDP of 15 W and a configurable TDP-down of of 10 W at 600 MHz, this Broadwell-based microprocessor is manufactured on Intel's 14 nm process.

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
4x32 KiB 8-way set associative (per core, write-back)
L1D$ 64 KiB
65,536 B
0.0625 MiB
4x32 KiB 8-way set associative (per core, write-back)
L2$ 512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
2x256 KiB 8-way set associative (per core, write-back)
L3$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
2x1 MiB 12-way set associative (shared)

Memory controller

Integrated Memory Controller
Type DDR3L-1333, DDR3L-1600, LPDDR3-1333, LPDDR3-1600
Controllers 1
Channels 2
ECC Support No
Max bandwidth 25,600 MB/s
Max memory 16 GiB

Graphics

Integrated Graphic Information
GPU Intel HD Graphics (Broadwell)
Displays 3
Frequency 100 MHz
0.1 GHz
100,000 KHz
Max frequency 800 MHz
0.8 GHz
800,000 KHz
DirectX 12
Intel Quick Sync Video
Intel InTru 3D
Intel Flexible Display Interface (FDI)
Intel Clear Video

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/3755u&oldid=27415"
Facts about "Celeron 3755U - Intel"
RDF feed
has featureintegrated gpu +
integrated gpuIntel HD Graphics (Broadwell) +
integrated gpu base frequency100 MHz (0.1 GHz, 100,000 KHz) +
integrated gpu max frequency800 MHz (0.8 GHz, 800,000 KHz) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description12-way set associative +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +