Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/xeon d/d-1540"
| Line 33: | Line 33: | ||
| cpuid = | | cpuid = | ||
| + | | isa family = x86 | ||
| + | | isa = x86-64 | ||
| microarch = Broadwell | | microarch = Broadwell | ||
| platform = Grangeville | | platform = Grangeville | ||
Revision as of 05:36, 3 December 2016
Template:mpu The Xeon D-1540 is a 64-bit octa-core x86-64 microserver SoC that was introduced by Intel in March of 2015. The D-1540 operates at 2 GHz with a turbo frequency of 2.6 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 45 W and can support up to 128 GB of RAM (DDR4).
Cache
- Main article: Broadwell § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 256 KiB 262,144 B 0.25 MiB |
8x32 KiB 8-way set associative (per core) |
| L1D$ | 256 KiB 262,144 B 0.25 MiB |
8x32 KiB 8-way set associative (per core) |
| L2$ | 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB |
8x256 KiB 8-way set associative (per core) |
| L3$ | 12 MiB 12,288 KiB 12,582,912 B 0.0117 GiB |
8x1.5 MiB (per core) |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR4-1600, DDR4-1867, DDR4-2133 |
| Controllers | 1 |
| Channels | 2 |
| ECC Support | Yes |
| Max memory | 128 GB |
Expansions
Networking
| Networking | |
| SFI interface | No |
| KR interface | No |
| KR4 interface | No |
| KX interface | No |
| KX4 interface | No |
| 10Base-T | No |
| 100Base-T | No |
| 1000Base-T | No |
| 10GBase-T | Yes |
Features
Facts about "Xeon D-1540 - Intel"
| l1d$ description | 8-way set associative + |
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| l3$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |