From WikiChip
Difference between revisions of "intel/xeon e5/e5-2699a v4"
< intel‎ | xeon e5

(Created page with "{{intel title|Xeon E5-2699A v4}} {{mpu | name = Xeon E5-2699A v4 | no image = Yes | image = | image size = | caption...")
 
(+cache)
Line 84: Line 84:
 
}}
 
}}
 
The '''Xeon E5-2699A v4''' is a {{arch|64}} [[docosa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for segment-optimized 2S environments (2U Square form factors). Operating at 2.4 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 
The '''Xeon E5-2699A v4''' is a {{arch|64}} [[docosa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for segment-optimized 2S environments (2U Square form factors). Operating at 2.4 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
 +
{{cache info
 +
|l1i cache=704 KiB
 +
|l1i break=22x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i extra=(per core, write-back)
 +
|l1d cache=704 KiB
 +
|l1d break=22x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d extra=(per core, write-back)
 +
|l2 cache=5.5 MiB
 +
|l2 break=22x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 extra=(per core, write-back)
 +
|l3 cache=55 MiB
 +
|l3 break=22x2.5 MiB
 +
|l3 desc=20-way set associative
 +
|l3 extra=(shared, per core, write-back)
 +
}}

Revision as of 03:02, 3 November 2016

Template:mpu The Xeon E5-2699A v4 is a 64-bit docosa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for segment-optimized 2S environments (2U Square form factors). Operating at 2.4 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 704 KiB
720,896 B
0.688 MiB
22x32 KiB 8-way set associative (per core, write-back)
L1D$ 704 KiB
720,896 B
0.688 MiB
22x32 KiB 8-way set associative (per core, write-back)
L2$ 5.5 MiB
5,632 KiB
5,767,168 B
0.00537 GiB
22x256 KiB 8-way set associative (per core, write-back)
L3$ 55 MiB
56,320 KiB
57,671,680 B
0.0537 GiB
22x2.5 MiB 20-way set associative (shared, per core, write-back)
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2699a_v4&oldid=26444"
Facts about "Xeon E5-2699A v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size704 KiB (720,896 B, 0.688 MiB) +
l1i$ description8-way set associative +
l1i$ size704 KiB (720,896 B, 0.688 MiB) +
l2$ description8-way set associative +
l2$ size5.5 MiB (5,632 KiB, 5,767,168 B, 0.00537 GiB) +
l3$ description20-way set associative +
l3$ size55 MiB (56,320 KiB, 57,671,680 B, 0.0537 GiB) +