Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "WikiChip:sandbox"
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| − | <table style="border: solid 1px #e5e5ff; width: | + | |
| − | <tr><th>L1$</th><td>128 KiB</td><td><table><tr><th>L1I$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th>L1D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr> | + | <table style="border: solid 1px #e5e5ff; width: 550px; margin: 0 10px 10px 10px; text-align: left; font-size: 12px;"><tr style="text-align: center; background: #ccffcc; font-size: 16px;"><td colspan="3"><span style="margin: 10px;">[[File:Sitemap font awesome.svg|25px]]</span><span style="font-weight: bold; font-size: 19px;">Cache Info {{#info: '''[[Cache]]''' is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a [[CPU]] by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.<br><br>The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.<br><br>Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.<br><br>Note: All units are in [[kibibytes]].}}</span><span style="float: right;">[[Special:FormEdit/Cache_info/{{FULLPAGENAME}}|<small><nowiki>[Edit Values]</nowiki></small>]]</span></td></tr> |
| − | <tr><th>L2$</th><td>128 KiB</td><td><table><tr><th>L2I$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th>L2D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr> | + | <tr><th style="min-width: 35px;">L1$</th><td>128 KiB</td><td><table><tr><th style="text-align: center; min-width: 50px;">L1I$</th><td style="min-width: 50px;">64 KiB</td><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th style="text-align: center; min-width: 50px;">L1D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr> |
| − | <tr><th>L3$</th><td>128 KiB</td><td><table><tr><th>L3I$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th>L3D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr> | + | <tr><th style="min-width: 35px;">L2$</th><td>128 KiB</td><td><table><tr><th style="text-align: center; min-width: 50px;">L2I$</th><td style="min-width: 50px;">64 KiB</td><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th style="text-align: center; min-width: 50px;">L2D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr> |
| − | <tr><th>L4$</th><td>128 KiB</td><td><table><tr><th>L4I$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th>L4D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr> | + | <tr><th style="min-width: 35px;">L3$</th><td>128 KiB</td><td><table><tr><th style="text-align: center; min-width: 50px;">L3I$</th><td style="min-width: 50px;">64 KiB</td><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th style="text-align: center; min-width: 50px;">L3D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr> |
| + | <tr><th style="min-width: 35px;">L4$</th><td>128 KiB</td><td><table><tr><th style="text-align: center; min-width: 50px;">L4I$</th><td style="min-width: 50px;">64 KiB</td><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr><tr><th style="text-align: center; min-width: 50px;">L4D$</th><td>64 KiB</td><td>1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr> | ||
| + | <tr style="text-align: center; background: #ccffcc; font-size: 12px;"><td colspan="3">Off-package cache support</td></tr> | ||
| + | <tr><th style="min-width: 35px;">Mobo</th><td>512 KiB</td><td><table><tr><td style="min-width: 75px;">1x64 KiB</td><td>2-way set associative</td><td>write-back</td></tr></table></td></tr> | ||
</table> | </table> | ||
Revision as of 04:03, 24 October 2016
Welcome to this sandbox page. Sandbox pages provide space to experiment with the process of editing.
| ssssssssssss | ||||||||
| DATA BUS I/O | D0 | 01 | 16 | CM-RAM0 | X | |||
| D1 | 02 | 15 | CM-RAM1 | X | ||||
| D2 | 03 | 14 | CM-RAM2 | X | ||||
| D3 | 04 | 13 | CM-RAM3 | X | ||||
| Vss | 05 | 12 | Vdd | X | ||||
| CLOCK PHASE 1/2 | Ø1 | 06 | 11 | CM-ROM | X | |||
| Ø2 | 07 | 10 | TEST | X | ||||
| SYNC | 08 | 09 | RESET | X | ||||
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
 Cache Info Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. [Edit Values]The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes. | ||||||||||||
| L1$ | 128 KiB |
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|---|---|---|---|---|---|---|---|---|---|---|---|---|
| L2$ | 128 KiB |
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| L3$ | 128 KiB |
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| L4$ | 128 KiB |
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| Off-package cache support | ||||||||||||
| Mobo | 512 KiB |
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