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Difference between revisions of "intel/celeron/n3050"
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== Cache ==
 
== Cache ==
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{{main|intel/microarchitectures/airmont#Memory_Hierarchy|l1=Airmont's Cache}}
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{{main|intel/microarchitectures/airmont#Memory_Hierarchy|l1=Airmont § Cache}}
 
{{cache info
 
{{cache info
−
|l1i cache=64 KB
+
|l1i cache=64 KiB
−
|l1i break=2x32 KB
+
|l1i break=2x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
 
|l1i extra=(per core)
 
|l1i extra=(per core)
−
|l1d cache=48 KB
+
|l1d cache=48 KiB
−
|l1d break=2x24 KB
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|l1d break=2x24 KiB
 
|l1d desc=6-way set associative
 
|l1d desc=6-way set associative
 
|l1d extra=(per core)
 
|l1d extra=(per core)
−
|l2 cache=1 MB
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|l2 cache=1 MiB
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|l2 break=1x1 MB
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|l2 break=1x1 MiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 extra=(per 2 cores)
 
|l2 extra=(per 2 cores)

Revision as of 22:22, 20 September 2016

Template:mpu The Celeron N3050 is a 64-bit dual-core system on a chip designed by Intel and introduced in early 2015. The N3050 is manufactured in 14 nm process based on the Airmont microarchitecture. This chip operates at 1.6 GHz with turbo mode of up to 2.16 GHz. This SoC incorporates the HD Graphics (Braswell) GPU which has 12 execution units and operates at 320 MHz with 600 MHz busts.

Cache

Main article: Airmont § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core)
L1D$ 48 KiB
49,152 B
0.0469 MiB
2x24 KiB 6-way set associative (per core)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
1x1 MiB 16-way set associative (per 2 cores)
L3$ 0 KiB
0 MiB
0 B
0 GiB
No L3$

Memory controller

Integrated Memory Controller
Type DDR3L-1600
Controllers 1
Channels 2
ECC Support No
Bandwidth (single) 12,800 MB/s
Bandwidth (dual) 25,600 MB/s
Max memory 8,192 MB

Graphics

Integrated Graphic Information
GPU HD Graphics (Braswell)
Execution Units 12
Displays 3
Frequency 320 MHz
0.32 GHz
320,000 KHz
Max frequency 600 MHz
0.6 GHz
600,000 KHz
Max memory 8 GB
"GB" is not declared as a valid unit of measurement for this property.
Output DisplayPort, Embedded DisplayPort, HDMI
DirectX 11.1
OpenGL 4.2
OpenCL 1.2
DVI 1.4b
HDMI 1.4b
DVI 1.4b
DP 1.1a
eDP 1.4
Max HDMI Res 3840x2160 @30 Hz, 2560x1600 @60 Hz
Max DVI Res 3840x2160 @30 Hz, 2560x1600 @60 Hz
Max DP Res 3840x2160 @30 Hz, 2560x1600 @60 Hz
Max eDP Res 2560x1440 @60 Hz
  • Video decode hardware acceleration including support for H.263, MPEG4, H.264, H.265 (HEVC), VP8, VP9, MVC, MPEG2, VC1, JPEG.
  • Video encode hardware acceleration including support for H.264, H.263, VP8, MVC, JPEG.

Expansions

Template:mpu expansions

  • USB:
    • USB 3.0: 4 Super Speed (SS) Ports @ 5 Gb/s
    • USB 2.0: 1 High Speed (HS) + 4 Multiplexed with SS Ports @ 5 Gb/s
    • USB HSIC: 2 High Speed Ports @ 480 Mb/s

Features

Template:mpu features

Storage

  • SD Card Interface: v3.0
  • SDIO Interface: v3.0
  • eMMC Interface: v4.5.1
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/n3050&oldid=25549"
Facts about "Celeron N3050 - Intel"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Celeron N3050 - Intel#io +
base frequency1,600 MHz (1.6 GHz, 1,600,000 kHz) +
bus typeIDI +
core count2 +
core nameBraswell +
core steppingC0 +
designerIntel +
familyCeleron +
first announcedMarch 2015 +
first launchedMarch 2015 +
full page nameintel/celeron/n3050 +
has featureintegrated gpu +, Advanced Encryption Standard Instruction Set Extension + and Enhanced SpeedStep Technology +
has intel enhanced speedstep technologytrue +
has locked clock multipliertrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpuHD Graphics (Braswell) +
integrated gpu base frequency320 MHz (0.32 GHz, 320,000 KHz) +
integrated gpu max frequency600 MHz (0.6 GHz, 600,000 KHz) +
integrated gpu max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB) +
isax86-64 +
isa familyx86 +
l1d$ description6-way set associative +
l1d$ size48 KiB (49,152 B, 0.0469 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ descriptionNo L3$ +
l3$ size0 MiB (0 KiB, 0 B, 0 GiB) +
last orderJune 8, 2018 +
last shipmentDecember 7, 2018 +
ldateMarch 2015 +
manufacturerIntel +
market segmentMobile +
max cpu count1 +
max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max operating temperature90 °C +
max pcie lanes4 +
microarchitectureAirmont +
min operating temperature0 °C +
model numberN3050 +
nameIntel Celeron N3050 +
part numberFH8066501715914 + and FH8066501715925 +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 107.00 (€ 96.30, £ 86.67, ¥ 11,056.31) +
s-specSR29H + and SR2A9 +
sdp4 W (4,000 mW, 0.00536 hp, 0.004 kW) +
seriesN3000 +
smp max ways1 +
tdp6 W (6,000 mW, 0.00805 hp, 0.006 kW) +
technologyCMOS +
thread count2 +
turbo frequency (1 core)2,160 MHz (2.16 GHz, 2,160,000 kHz) +
used byASUSPRO P2520SA +, ASUS EeeBook E202SA +, Acer Aspire ES1-531 + and ASUS TP200SA DH04T 11.6" transformer book +
word size64 bit (8 octets, 16 nibbles) +