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Difference between revisions of "amd/k6-iii/amd-k6-iii-333afr"
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m (David moved page amd/k6-iii/k6-iii-333afr to amd/k6-iii/amd-k6-iii-333afr: corrected name)
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{{amd title|K6-III/333AFR}}
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{{amd title|AMD-K6-III/333AFR}}
 
{{mpu
 
{{mpu
| name                = K6-III/333AFR
+
| name                = AMD-K6-III/333AFR
 
| no image            =  
 
| no image            =  
 
| image              = Ic-photo-AMD--AMD-K6-III 333AFK-(K6-CPU).jpg
 
| image              = Ic-photo-AMD--AMD-K6-III 333AFK-(K6-CPU).jpg
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| designer            = AMD
 
| designer            = AMD
 
| manufacturer        = AMD
 
| manufacturer        = AMD
| model number        = K6-III/333AFR
+
| model number        = AMD-K6-III/333AFR
 
| part number        = AMD-K6-III/333AFR
 
| part number        = AMD-K6-III/333AFR
 
| part number 1      =  
 
| part number 1      =  
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| socket 0 2 type    = PGA-321
 
| socket 0 2 type    = PGA-321
 
}}
 
}}
'''K6-III/333AFR''' is a {{arch|32}} [[x86]] desktop microprocessor designed by [[AMD]] and introduced in early [[1999]]. This MPU which was manufactured on a [[0.25 µm process]], based on {{amd|microarchitectures/k6-iii|K6-III microarchitecture}}, operated at 333 MHz with a bus of 95 MHz. While default to a 95 MHz bus ([[Super 7]]), this model can also operate at the old [[Socket 7]] bus speed of 66 MHz (multiplier of 5).
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'''AMD-K6-III/333AFR''' is a {{arch|32}} [[x86]] desktop microprocessor designed by [[AMD]] and introduced in early [[1999]]. This MPU which was manufactured on a [[0.25 µm process]], based on {{amd|microarchitectures/k6-iii|K6-III microarchitecture}}, operated at 333 MHz with a bus of 95 MHz. While default to a 95 MHz bus ([[Super 7]]), this model can also operate at the old [[Socket 7]] bus speed of 66 MHz (multiplier of 5).
  
 
== Cache ==
 
== Cache ==

Revision as of 05:57, 8 September 2016

Template:mpu AMD-K6-III/333AFR is a 32-bit x86 desktop microprocessor designed by AMD and introduced in early 1999. This MPU which was manufactured on a 0.25 µm process, based on K6-III microarchitecture, operated at 333 MHz with a bus of 95 MHz. While default to a 95 MHz bus (Super 7), this model can also operate at the old Socket 7 bus speed of 66 MHz (multiplier of 5).

Cache

Main article: K6-III § Cache

L3$ can be 512 KB to 2 MB, depending on manufacturer and motherboard model. L3$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KB
"KB" is not declared as a valid unit of measurement for this property.
1x32 KB 2-way set associative
L1D$ 32 KB
"KB" is not declared as a valid unit of measurement for this property.
1x32 KB 2-way set associative
L2$ 256 KB
"KB" is not declared as a valid unit of measurement for this property.
1x256 4-way set associative (shared)

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Auto-power down state
  • Stop clock state
  • Halt state
l1d$ description2-way set associative +
l1i$ description2-way set associative +
l2$ description4-way set associative +