From WikiChip
Difference between revisions of "pezy/pezy-scx/pezy-sc2"
Line 1: | Line 1: | ||
{{pezy title|PEZY-SC2}} | {{pezy title|PEZY-SC2}} | ||
{{mpu | {{mpu | ||
+ | | future = Yes | ||
| name = PEZY-SC2 | | name = PEZY-SC2 | ||
| no image = Yes | | no image = Yes |
Revision as of 00:33, 4 December 2016
Template:mpu PEZY-SC2 (PEZY Super Computer 2) is third generation many-core microprocessor developed by PEZY set to be released in late 2016 or early 2017. The SC2 is planned to have 4096 cores, 4 times as many cores as its predecessor. Unlike the PEZY-SC which had 2 ARM926, the SC2 will be replaced by 12 MIPS64 cores.
PEZY-SC2 is planned to operate at 1 GHz and consume around 100 W while delivering performance in the order of 16.4 TFLOPS (single-precision) and 8.2 TFLOPS (double precision). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's 16 nm process.