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Difference between revisions of "pezy/pezy-scx/pezy-scnp"
< pezy‎ | pezy-scx

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|l1i cache=2 MB
 
|l1i cache=2 MB
 
|l1i break=1024x2 KB
 
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|l1i desc=
 
 
|l1i extra=(per processor element)
 
|l1i extra=(per processor element)
 
|l1d cache=1 MB
 
|l1d cache=1 MB
 
|l1d break=512x2 KB
 
|l1d break=512x2 KB
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|l1d desc=
 
 
|l1d extra=(per 2 processor elements)
 
|l1d extra=(per 2 processor elements)
 
|l2 cache=4 MB
 
|l2 cache=4 MB
 
|l2 break=4x2 MB
 
|l2 break=4x2 MB
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|l2 desc=
 
 
|l2 extra=(per city)
 
|l2 extra=(per city)
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|l3 cache=8 MB
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|l3 cache=8 MiB
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|l3 break=4x2 MB
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|l3 extra=(per prefecture)
 
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Revision as of 02:00, 19 September 2016

Template:mpu PEZY-SCnp (SC - Super Computer; np - New Package) is a revised version of the PEZY-SC model by PEZY introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZY-SC, the SCnp is also manufactured on TSMC's 28HPC+ (28 nm process).

Architecture

Main article: PEZY-SC §Architecture

The PEZY-SCnp's architecture is identical to the PEZY-SC.

Cache

PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32KB (2x) and 64KB L2$ (shared).

Cache Info [Edit Values]
L1I$ 2 MB
"MB" is not declared as a valid unit of measurement for this property.
 		1024x2 KB (per processor element)
L1D$ 1 MB
"MB" is not declared as a valid unit of measurement for this property.
 		512x2 KB (per 2 processor elements)
L2$ 4 MB
"MB" is not declared as a valid unit of measurement for this property.
 		4x2 MB (per city)
L3$ 8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
4x2 MiB (per prefecture)

Memory controller

Integrated Memory Controller
Type DDR4-1866
Controllers 1
Channels 8
Bandwidth (single) 14,933 MB/s
Bandwidth (dual) 29,866 MB/s
Bandwidth (quad) 59,732 MB/s
Bandwidth (octa) 119,464 MB/s

Expansions

Template:mpu expansions

Retrieved from "https://en.wikichip.org/w/index.php?title=pezy/pezy-scx/pezy-scnp&oldid=25129"
Facts about "PEZY-SCnp - PEZY"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
PEZY-SCnp - PEZY#package + and PEZY-SCnp - PEZY#pcie +
base frequency766.66 MHz (0.767 GHz, 766,660 kHz) +
core count1,024 +
core voltage0.95 V (9.5 dV, 95 cV, 950 mV) +
designerPEZY +
familyPEZY-SCx +
first announcedMay 6, 2016 +
first launchedMay 6, 2016 +
full page namepezy/pezy-scx/pezy-scnp +
has ecc memory supporttrue +
instance ofmicroprocessor +
l1$ size64 KiB (65,536 B, 0.0625 MiB) + and 3,072 KiB (3,145,728 B, 3 MiB) +
l1d$ descriptionper 2 processor elements +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) + and 1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ descriptionper processor element +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) + and 2,048 KiB (2,097,152 B, 2 MiB) +
l2$ descriptionper city +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + and 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ descriptionper prefecture +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldateMay 6, 2016 +
main imageFile:pezy-scnp (front).png +
manufacturerTSMC +
market segmentSupercomputer +
max memory bandwidth127.156 GiB/s (130,207.744 MiB/s, 136.533 GB/s, 136,532.715 MB/s, 0.124 TiB/s, 0.137 TB/s) +
max memory channels8 +
model numberPEZY-SCnp +
namePEZY-SCnp +
packageFCBGA-2397 +
peak flops (double-precision)1,570,133,331,968 FLOPS (1,570,133,331.968 KFLOPS, 1,570,133.332 MFLOPS, 1,570.133 GFLOPS, 1.57 TFLOPS, 0.00157 PFLOPS, 1.570133e-6 EFLOPS, 1.570133e-9 ZFLOPS) +
peak flops (single-precision)3,140,266,663,936 FLOPS (3,140,266,663.936 KFLOPS, 3,140,266.664 MFLOPS, 3,140.267 GFLOPS, 3.14 TFLOPS, 0.00314 PFLOPS, 3.140267e-6 EFLOPS, 3.140267e-9 ZFLOPS) +
power dissipation100 W (100,000 mW, 0.134 hp, 0.1 kW) +
power dissipation (average)70 W (70,000 mW, 0.0939 hp, 0.07 kW) +
process28 nm (0.028 μm, 2.8e-5 mm) +
supported memory typeDDR4-2133 +
technologyCMOS +
thread count8,192 +