From WikiChip
Difference between revisions of "intel/celeron/j3455"
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|l3 cache=0 KB | |l3 cache=0 KB | ||
|l3 desc=No L3$ | |l3 desc=No L3$ | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{integrated memory controller | ||
+ | | type = LPDDR3-1333 | ||
+ | | type 2 = LPDDR3-1600 | ||
+ | | type 3 = LPDDR3-2400 | ||
+ | | type 4 = DDR3L-1333 | ||
+ | | type 5 = DDR3L-1600 | ||
+ | | type 6 = DDR3L-1867 | ||
+ | | type 7 = LPDDR4-1600 | ||
+ | | type 8 = LPDDR4-2133 | ||
+ | | type 9 = LPDDR4-2400 | ||
+ | | controllers = 1 | ||
+ | | channels = 2 | ||
+ | | ecc support = No | ||
+ | | bandwidth schan = 19,200 MB/s | ||
+ | | bandwidth dchan = 38,400 MB/s | ||
+ | | max memory = 8,192 MB | ||
}} | }} |
Revision as of 23:20, 5 September 2016
Template:mpu Celeron J3455 is a quad-core 64-bit x86 desktop microprocessor introduced by Intel in 2016. The processor is based on Goldmont microarchitecture and is manufactured on a 14 nm process. The chip operates at 1.5 GHz with burst frequency of 2.3 GHz and has a TDP of 10 W. This MPU incorporates Intel's HD Graphics 500 GPU operating at 250 MHz with a burst frequency of 750 MHz.
Cache
- Main article: Goldmont's Cache
Cache Info [Edit Values] | ||
L1I$ | 128 KB "KB" is not declared as a valid unit of measurement for this property. |
4x32 KB 8-way set associative (per core) |
L1D$ | 96 KB "KB" is not declared as a valid unit of measurement for this property. |
4x24 KB 6-way set associative (per core) |
L2$ | 2 MB "MB" is not declared as a valid unit of measurement for this property. |
2x1 MB 16-way set associative (per 2 cores) |
L3$ | 0 KB "KB" is not declared as a valid unit of measurement for this property. |
No L3$ |
Memory controller
Integrated Memory Controller | |
Type | LPDDR3-1333, LPDDR3-1600, LPDDR3-2400, DDR3L-1333, DDR3L-1600, DDR3L-1867, LPDDR4-1600, LPDDR4-2133, LPDDR4-2400 |
Controllers | 1 |
Channels | 2 |
ECC Support | No |
Bandwidth (single) | 19,200 MB/s |
Bandwidth (dual) | 38,400 MB/s |
Max memory | 8,192 MB |
Facts about "Celeron J3455 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron J3455 - Intel#io + |
base frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) + |
clock multiplier | 15 + |
core count | 4 + |
core name | Apollo Lake + |
core stepping | B1 + |
designer | Intel + |
device id | 0x5A85 + |
family | Celeron + |
first announced | August 30, 2016 + |
first launched | August 30, 2016 + |
full page name | intel/celeron/j3455 + |
has extended page tables support | true + |
has feature | integrated gpu +, Advanced Encryption Standard Instruction Set Extension +, Burst Performance Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology + and Extended Page Tables + |
has intel burst performance technology | true + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | HD Graphics 500 + |
integrated gpu base frequency | 250 MHz (0.25 GHz, 250,000 KHz) + |
integrated gpu max frequency | 750 MHz (0.75 GHz, 750,000 KHz) + |
integrated gpu max memory | 8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB) + |
l1d$ description | 6-way set associative + |
l1d$ size | 96 KiB (98,304 B, 0.0938 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ description | No L3$ + |
l3$ size | 0 MiB (0 KiB, 0 B, 0 GiB) + |
ldate | August 30, 2016 + |
manufacturer | Intel + |
market segment | Desktop + |
max cpu count | 1 + |
max junction temperature | 378.15 K (105 °C, 221 °F, 680.67 °R) + |
max memory | 8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) + |
max pcie lanes | 6 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Goldmont + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | J3455 + |
name | Celeron J3455 + |
part number | FH8066802986102 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 107.00 (€ 96.30, £ 86.67, ¥ 11,056.31) + |
s-spec | SR2Z9 + |
series | J Series + |
smp max ways | 1 + |
tdp | 10 W (10,000 mW, 0.0134 hp, 0.01 kW) + |
technology | CMOS + |
thread count | 4 + |
turbo frequency (1 core) | 2,300 MHz (2.3 GHz, 2,300,000 kHz) + |
turbo frequency (4 cores) | 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |