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Difference between revisions of "intrinsity/fastmath/fastmath-lp"
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Revision as of 16:28, 3 July 2016
Template:mpu The FastMATH-LP was a microprocessor developed by Intrinsity operating at 1 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.
Cache
- Main article: FastMATH § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KB "KB" is not declared as a valid unit of measurement for this property. |
1x16 KB 256 blocks × 16 words/block |
| L1D$ | 16 KB "KB" is not declared as a valid unit of measurement for this property. |
1x16 KB 256 blocks × 16 words/block write-through or write-back mode |
| L2$ | 1 MB "MB" is not declared as a valid unit of measurement for this property. |
1x1 MB 4-way set associative (configurable as SRAM in 256 KB increments) |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR-400 |
| Controllers | 1 |
| Channels | 2 |
| Max memory | 1 GB |
Matrix and Vector Unit
- SIMD architecture
- Operates on 4x4 array of 32-bit elements
- Fixed-point matrix, vector, and scalar data types
Features
- JTAG interface
- 8-bit or 32-bit wide bus operates up to 66 MHz
Facts about "FastMATH-LP - Intrinsity"
| base frequency | 1,000 MHz (1 GHz, 1,000,000 kHz) + |
| bus rate | 4,000 MT/s (4 GT/s, 4,000,000 kT/s) + |
| bus speed | 500 MHz (0.5 GHz, 500,000 kHz) + |
| bus type | RapidIO + |
| core count | 1 + |
| core voltage | 0.85 V (8.5 dV, 85 cV, 850 mV) + |
| designer | Intrinsity + |
| family | FastMATH + |
| first announced | 2002 + |
| first launched | 2003 + |
| full page name | intrinsity/fastmath/fastmath-lp + |
| has feature | JTAG + |
| instance of | microprocessor + |
| l1d$ description | 256 blocks × 16 words/block + |
| l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l1i$ description | 256 blocks × 16 words/block + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| ldate | 2003 + |
| main image |  + |
| manufacturer | TSMC + |
| market segment | Embedded + |
| max memory | 1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) + |
| microarchitecture | FashMATH + |
| model number | FastMATH-LP + |
| name | FastMATH-LP + |
| power dissipation | 6 W (6,000 mW, 0.00805 hp, 0.006 kW) + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| technology | Dynamic CMOS + |
| thread count | 1 + |
| word size | 32 bit (4 octets, 8 nibbles) + |
