Semiconductor & Computer Engineering
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Difference between revisions of "intrinsity/fastmath"
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=== Manuals === | === Manuals === | ||
| − | * [[:File:FastMATH Product Brief.pdf| | + | * [[:File:FastMATH Product Brief.pdf|FastMATH Product Brief]] |
=== White Paper === | === White Paper === | ||
Revision as of 00:16, 3 July 2016
| FastMATH | |
| |
| FastMATH and FastMIPS chips | |
| Developer | Intrinsity |
| Manufacturer | TSMC |
| Type | Microprocessors |
| Introduction | 2000 (announced) 2002 (launch) |
| Architecture | 32-bit vector/matrix math processor + RISC cpu |
| Word size | 32 bit 4 octets
8 nibbles |
| Process | 130 nm 0.13 μm
1.3e-4 mm |
| Technology | CMOS |
| Clock | 1 GHz-3 GHz |
| Package | CBGA-670 |
FastMATH was a family of matrix and vector math processors with an on-die RISC CPUs introduced by Intrinsity. The chips were developed using Intrinsity's own proprietary Fast14 technology.
Documents
Manuals
White Paper
Facts about "FastMATH - Intrinsity"
| designer | Intrinsity + |
| first announced | 2000 + |
| first launched | 2002 + |
| full page name | intrinsity/fastmath + |
| instance of | microprocessor family + |
| main designer | Intrinsity + |
| manufacturer | TSMC + |
| name | FastMATH + |
| package | CBGA-670 + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |