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Difference between revisions of "exponential technology/x704/533"
< exponential technology‎ | x704

(Cache)
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== Cache ==
 
== Cache ==
 
{{main|exponential_technology/microarchitectures/x704#Memory_Hierarchy|l1=X704 § Cache}}
 
{{main|exponential_technology/microarchitectures/x704#Memory_Hierarchy|l1=X704 § Cache}}
Level 3 can be provided externally with cache size of 512 KB to 2 MB.
+
Level 3 can be provided externally with cache size of 512 KiB to 2 MiB.
 
{{cache info
 
{{cache info
|l1i cache=2 KB
+
|l1i cache=2 KiB
|l1i break=1x2 KB
+
|l1i break=1x2 KiB
 
|l1i desc=direct mapped
 
|l1i desc=direct mapped
 
|l1i extra=
 
|l1i extra=
|l1d cache=2 KB
+
|l1d cache=2 KiB
|l1d break=1x2 KB
+
|l1d break=1x2 KiB
 
|l1d desc=direct mapped
 
|l1d desc=direct mapped
 
|l1d extra=
 
|l1d extra=
|l2 cache=32 KB
+
|l2 cache=32 KiB
|l2 break=1x32 KB
+
|l2 break=1x32 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 extra=
 
|l2 extra=

Revision as of 23:56, 20 September 2016

Template:mpu X704 533 MHz was a PowerPC-compatible microprocessor operating at 533 MHz announced in January 1997 by Exponential Technology. This was exponential flagship model, however the company folded before the model ever reaching market (See X704 § History).

Cache

Main article: X704 § Cache

Level 3 can be provided externally with cache size of 512 KiB to 2 MiB.

Cache Info [Edit Values]
L1I$ 2 KiB
2,048 B
0.00195 MiB
1x2 KiB direct mapped
L1D$ 2 KiB
2,048 B
0.00195 MiB
1x2 KiB direct mapped
L2$ 32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
1x32 KiB 8-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

  • Fully PowerPC 60x-compatible architecture
  • IEEE 1149.1-compliant JTAG test access port
  • IEEE 754-compliant single-precision and double-precision arithmetic
  • Support for standard PowerPC 60X bus with 64 bits of data and 32 bits of address
  • Support for all PowerPC cache operations
  • Support for PowerEndian and BigEndian modes

Documents

Manuals

See also

l1d$ descriptiondirect mapped +
l1i$ descriptiondirect mapped +
l2$ description8-way set associative +