From WikiChip
Difference between revisions of "intel/microarchitectures/cannon lake"
Line 14: | Line 14: | ||
| successor link = intel/microarchitectures/icelake | | successor link = intel/microarchitectures/icelake | ||
}} | }} | ||
− | '''Cannonlake''' is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannonlake is expected to be fabricated using a [[10 nm process]]. | + | '''Cannonlake''' ('''CNL''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannonlake is expected to be fabricated using a [[10 nm process]]. |
Revision as of 09:13, 31 August 2016
Edit Values | |
Cannonlake µarch | |
General Info |
Cannonlake (CNL) is a planned microarchitecture by Intel as a successor to Kaby Lake. Cannonlake is expected to be fabricated using a 10 nm process.
Facts about "Cannon Lake - Microarchitectures - Intel"
codename | Cannon Lake + |
core count | 2 + |
designer | Intel + |
first launched | May 15, 2018 + |
full page name | intel/microarchitectures/cannon lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cannon Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |