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Difference between revisions of "intel/xeon e7/e7-4820"
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'''Xeon E7-4820''' is a {{arch|64}} [[x86]] data center microprocessor that supports up to 4 sockets. This first generation {{intel|Xeon E7}} processor, {{intel|Westmere|Westmere}}-based, operates at a base frequency of 2 GHz with {{intel|turbo boost technology|turob}} frequency of 2.266 GHz for 2 active cores. This chip has a TDP of 105 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory.
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'''Xeon E7-4820''' is a {{arch|64}} octa-core [[x86]] data center microprocessor that supports up to 4 sockets. This first generation {{intel|Xeon E7}} processor, {{intel|Westmere|Westmere}}-based, operates at a base frequency of 2 GHz with {{intel|turbo boost technology|turob}} frequency of 2.266 GHz for 2 active cores. This chip has a TDP of 105 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory.
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== Cache ==
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{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}}
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{{cache info
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|l1i cache=256 KB
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|l1i break=8x32 KB
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|l1i desc=4-way set associative
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|l1i extra=(per core)
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|l1d cache=256 KB
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|l1d break=8x32 KB
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|l1d desc=8-way set associative
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|l1d extra=(per core)
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|l2 cache=2 MB
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|l2 break=8x256 KB
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|l2 desc=8-way set associative
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|l2 extra=(per core)
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|l3 cache=18 MB
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|l3 break=
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|l3 desc=16-way set associative
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|l3 extra=
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}}
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== Graphics ==
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This SoC has no integrated graphics processing unit.
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== Memory controller ==
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{{integrated memory controller
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| type              = DDR3-800
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| type 2            = DDR3-978
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| type 3            = DDR3-1066
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| controllers        = 1
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| channels          = 4
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| ecc support        = Yes
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| max bandwidth      =
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| bandwidth schan    =
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| bandwidth dchan    =
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| max memory        = 2048 GB
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}}
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== Features ==
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{{mpu features
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| em64t      = Yes
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| nx          = Yes
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| txt        = Yes
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| tsx        =
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| vpro        =
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| ht          = Yes
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| tbt1        = Yes
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| tbt2        =
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| bpt        =
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| vt-x        = Yes
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| vt-d        = yes
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| ept        = Yes
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| mmx        = Yes
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| sse        = Yes
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| sse2        = Yes
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| sse3        = Yes
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| ssse3      = Yes
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| sse4.1      = Yes
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| sse4.2      = Yes
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| aes        = Yes
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| pclmul      =
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| avx        =
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| avx2        =
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| bmi        =
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| bmi1        =
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| bmi2        =
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| f16c        =
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| fma3        =
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| mpx        =
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| sgx        =
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| eist        = Yes
 +
| secure key  =
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| os guard    =
 +
| intel at    =
 +
}}

Revision as of 23:01, 12 June 2016

Template:mpu Xeon E7-4820 is a 64-bit octa-core x86 data center microprocessor that supports up to 4 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2 GHz with turob frequency of 2.266 GHz for 2 active cores. This chip has a TDP of 105 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory.

Cache

Main article: Westmere § Cache
Cache Info [Edit Values]
L1I$ 256 KB
"KB" is not declared as a valid unit of measurement for this property.
 		8x32 KB 4-way set associative (per core)
L1D$ 256 KB
"KB" is not declared as a valid unit of measurement for this property.
 		8x32 KB 8-way set associative (per core)
L2$ 2 MB
"MB" is not declared as a valid unit of measurement for this property.
 		8x256 KB 8-way set associative (per core)
L3$ 18 MB
"MB" is not declared as a valid unit of measurement for this property.
 		16-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3-800, DDR3-978, DDR3-1066
Controllers 1
Channels 4
ECC Support Yes
Max memory 2048 GB

Features

Template:mpu features

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l1d$ description8-way set associative +
l1i$ description4-way set associative +
l2$ description8-way set associative +
l3$ description16-way set associative +