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Difference between revisions of "intel/xeon e7/e7-4820"
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− | '''Xeon E7-4820''' is a {{arch|64}} [[x86]] data center microprocessor that supports up to 4 sockets. This first generation {{intel|Xeon E7}} processor, {{intel|Westmere|Westmere}}-based, operates at a base frequency of 2 GHz with {{intel|turbo boost technology|turob}} frequency of 2.266 GHz for 2 active cores. This chip has a TDP of 105 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory. | + | '''Xeon E7-4820''' is a {{arch|64}} octa-core [[x86]] data center microprocessor that supports up to 4 sockets. This first generation {{intel|Xeon E7}} processor, {{intel|Westmere|Westmere}}-based, operates at a base frequency of 2 GHz with {{intel|turbo boost technology|turob}} frequency of 2.266 GHz for 2 active cores. This chip has a TDP of 105 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory. |
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | ||
+ | {{cache info | ||
+ | |l1i cache=256 KB | ||
+ | |l1i break=8x32 KB | ||
+ | |l1i desc=4-way set associative | ||
+ | |l1i extra=(per core) | ||
+ | |l1d cache=256 KB | ||
+ | |l1d break=8x32 KB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d extra=(per core) | ||
+ | |l2 cache=2 MB | ||
+ | |l2 break=8x256 KB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 extra=(per core) | ||
+ | |l3 cache=18 MB | ||
+ | |l3 break= | ||
+ | |l3 desc=16-way set associative | ||
+ | |l3 extra= | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | This SoC has no integrated graphics processing unit. | ||
+ | |||
+ | == Memory controller == | ||
+ | {{integrated memory controller | ||
+ | | type = DDR3-800 | ||
+ | | type 2 = DDR3-978 | ||
+ | | type 3 = DDR3-1066 | ||
+ | | controllers = 1 | ||
+ | | channels = 4 | ||
+ | | ecc support = Yes | ||
+ | | max bandwidth = | ||
+ | | bandwidth schan = | ||
+ | | bandwidth dchan = | ||
+ | | max memory = 2048 GB | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{mpu features | ||
+ | | em64t = Yes | ||
+ | | nx = Yes | ||
+ | | txt = Yes | ||
+ | | tsx = | ||
+ | | vpro = | ||
+ | | ht = Yes | ||
+ | | tbt1 = Yes | ||
+ | | tbt2 = | ||
+ | | bpt = | ||
+ | | vt-x = Yes | ||
+ | | vt-d = yes | ||
+ | | ept = Yes | ||
+ | | mmx = Yes | ||
+ | | sse = Yes | ||
+ | | sse2 = Yes | ||
+ | | sse3 = Yes | ||
+ | | ssse3 = Yes | ||
+ | | sse4.1 = Yes | ||
+ | | sse4.2 = Yes | ||
+ | | aes = Yes | ||
+ | | pclmul = | ||
+ | | avx = | ||
+ | | avx2 = | ||
+ | | bmi = | ||
+ | | bmi1 = | ||
+ | | bmi2 = | ||
+ | | f16c = | ||
+ | | fma3 = | ||
+ | | mpx = | ||
+ | | sgx = | ||
+ | | eist = Yes | ||
+ | | secure key = | ||
+ | | os guard = | ||
+ | | intel at = | ||
+ | }} |
Revision as of 23:01, 12 June 2016
Template:mpu Xeon E7-4820 is a 64-bit octa-core x86 data center microprocessor that supports up to 4 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2 GHz with turob frequency of 2.266 GHz for 2 active cores. This chip has a TDP of 105 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory.
Contents
Cache
- Main article: Westmere § Cache
Cache Info [Edit Values] | ||
L1I$ | 256 KB "KB" is not declared as a valid unit of measurement for this property. |
8x32 KB 4-way set associative (per core) |
L1D$ | 256 KB "KB" is not declared as a valid unit of measurement for this property. |
8x32 KB 8-way set associative (per core) |
L2$ | 2 MB "MB" is not declared as a valid unit of measurement for this property. |
8x256 KB 8-way set associative (per core) |
L3$ | 18 MB "MB" is not declared as a valid unit of measurement for this property. |
16-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR3-800, DDR3-978, DDR3-1066 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max memory | 2048 GB |
Features
Facts about "Xeon E7-4820 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E7-4820 - Intel#package + |
base frequency | 1,999.99 MHz (2 GHz, 1,999,990 kHz) + |
bus rate | 5,860 MT/s (5.86 GT/s, 5,860,000 kT/s) + |
bus type | QPI + |
chipset | Boxboro + |
clock multiplier | 15 + |
core count | 8 + |
core family | 6 + |
core model | 47 + |
core name | Westmere EX + |
core stepping | A2 + |
core voltage | 1.35 V (13.5 dV, 135 cV, 1,350 mV) + |
cpuid | 206F2 + |
designer | Intel + |
die area | 513 mm² (0.795 in², 5.13 cm², 513,000,000 µm²) + |
family | Xeon E7 + |
first announced | April 5, 2011 + |
first launched | April 5, 2011 + |
full page name | intel/xeon e7/e7-4820 + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 1.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 1 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + |
last order | August 21, 2015 + |
last shipment | February 5, 2016 + |
ldate | April 5, 2011 + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 337.15 K (64 °C, 147.2 °F, 606.87 °R) + |
max cpu count | 4 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
max memory bandwidth | 31.77 GiB/s (32,532.48 MiB/s, 34.113 GB/s, 34,112.778 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 4 + |
max storage temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
microarchitecture | Westmere + |
min case temperature | 278.15 K (5 °C, 41 °F, 500.67 °R) + |
min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
model number | E7-4820 + |
name | Xeon E7-4820 + |
package | FCLGA-8 + |
part number | AT80615005772AC + |
platform | Boxboro + |
process | 32 nm (0.032 μm, 3.2e-5 mm) + |
release price | $ 1,446.00 (€ 1,301.40, £ 1,171.26, ¥ 149,415.18) + |
s-spec | SLC3G + |
series | E7-4800 + |
smp max ways | 4 + |
supported memory type | DDR3-1066 + |
tdp | 105 W (105,000 mW, 0.141 hp, 0.105 kW) + |
technology | CMOS + |
thread count | 16 + |
transistor count | 2,600,000,000 + |
turbo frequency (1 core) | 2,266.66 MHz (2.267 GHz, 2,266,660 kHz) + |
turbo frequency (2 cores) | 2,266.66 MHz (2.267 GHz, 2,266,660 kHz) + |
turbo frequency (3 cores) | 2,133.33 MHz (2.133 GHz, 2,133,330 kHz) + |
turbo frequency (4 cores) | 2,133.33 MHz (2.133 GHz, 2,133,330 kHz) + |
turbo frequency (5 cores) | 2,133.33 MHz (2.133 GHz, 2,133,330 kHz) + |
turbo frequency (6 cores) | 2,133.33 MHz (2.133 GHz, 2,133,330 kHz) + |
turbo frequency (7 cores) | 2,133.33 MHz (2.133 GHz, 2,133,330 kHz) + |
turbo frequency (8 cores) | 2,133.33 MHz (2.133 GHz, 2,133,330 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |