From WikiChip
Difference between revisions of "amd/am486/am486dxl2-80"
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| bus type = FSB | | bus type = FSB | ||
| bus speed = 40 MHz | | bus speed = 40 MHz | ||
− | | bus rate = | + | | bus rate = 40 MT/s |
| clock multiplier = 2 | | clock multiplier = 2 | ||
| cpuid = | | cpuid = |
Revision as of 04:40, 17 May 2016
Template:mpu Am486DXL2-80 was an 80486-compatible microprocessor introduced by AMD in late 1993. This processor had a clock multiplier of 2 having base frequency of 80 MHz with a bus frequency of 40 MHz. This is a low voltage only.
Cache
- Main article: 80486 § Cache
Cache Info [Edit Values] | ||
L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.
See also
Facts about "Am486DXL2-80 - AMD"
base frequency | 80 MHz (0.08 GHz, 80,000 kHz) + |
bus rate | 40 MT/s (0.04 GT/s, 40,000 kT/s) + |
bus speed | 40 MHz (0.04 GHz, 40,000 kHz) + |
bus type | FSB + |
clock multiplier | 2 + |
core count | 1 + |
core name | 486DXL2 + |
core voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
core voltage tolerance | 0.3 V + |
designer | AMD + |
family | Am486 + |
first launched | September 1993 + |
full page name | amd/am486/am486dxl2-80 + |
instance of | microprocessor + |
l1$ description | 4-way set associative + |
l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
ldate | September 1993 + |
manufacturer | AMD + |
market segment | Desktop + |
max cpu count | 1 + |
max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
max operating temperature | 85 °C + |
microarchitecture | 80486 + |
min operating temperature | 0 °C + |
model number | Am486DXL2-80 + |
name | Am486DXL2-80 + |
part number | A8048DXL2-80 + |
process | 700 nm (0.7 μm, 7.0e-4 mm) + |
series | Am486DX2 + |
smp max ways | 1 + |
technology | CMOS + |
transistor count | 1,200,000 + |
word size | 32 bit (4 octets, 8 nibbles) + |