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Difference between revisions of "majority gate"
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The '''majority gate''' ('''MAJ gate''') is a [[logic gate]] that implements the [[majority function]] - a device that outputs a [[HIGH]] when the majority of its inputs are HIGH, otherwise it outputs a [[LOW]]. | The '''majority gate''' ('''MAJ gate''') is a [[logic gate]] that implements the [[majority function]] - a device that outputs a [[HIGH]] when the majority of its inputs are HIGH, otherwise it outputs a [[LOW]]. | ||
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| + | == Applications == | ||
| + | {{empty section}} | ||
== MAJ3 == | == MAJ3 == | ||
<span style="display:inline-block;float: right; margin: 5px;">[[File:MAJ3 gate.svg|250px]]</span> | <span style="display:inline-block;float: right; margin: 5px;">[[File:MAJ3 gate.svg|250px]]</span> | ||
| − | A 3-input MAJ gate (MAJ3) can be implemented as <math>(a \land b) \lor (a \land c) \lor (b \land c)</math>. However the naive implementation will result in up to 30 transistors. Since <math>\text{MAJ}(a, b, c) = \overline{\overline{\text{MAJ}(a, b, c)}}</math>, we can | + | A 3-input MAJ gate (MAJ3) can be implemented as <math>(a \land b) \lor (a \land c) \lor (b \land c)</math>. |
| + | ===CMOS=== | ||
| + | However the naive implementation will result in up to 30 transistors. Since <math>\text{MAJ}(a, b, c) = \overline{\overline{\text{MAJ}(a, b, c)}}</math>, we can defined as <math>\text{MAJ}(a, b, c) = \overline{\overline{(a \land b) \lor (a \land c) \lor (b \land c)}}</math> and that can be implemented using a single [[AOI|AOI222]] which is defined as <math>\text{AOI222}(a, b, c, d, e, f) = \overline{(a \land b) \lor (c \land d) \lor (e \land f)}</math> - i.e. <math>\text{MAJ}(a, b, c) = \overline{AOI222(a, b, c, a, b, c)}</math>. It can also be implemented using a [[OAI|OAI222]] gate the very same way. Since <math>\text{OAI222}(a, b, c, d, e, f) = \overline{(a \lor b) \land (c \lor d) \land (e \lor f)}</math>, then <math>\text{MAJ}(a, b, c) = \overline{OAI222(a, b, c, a, b, c)}</math> | ||
| + | [[File:maj gate (cmos).svg|left|200px]] | ||
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The majority gate (MAJ gate) is a logic gate that implements the majority function - a device that outputs a HIGH when the majority of its inputs are HIGH, otherwise it outputs a LOW.
Applications
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This section is empty; you can help add the missing info by editing this page. |
MAJ3
A 3-input MAJ gate (MAJ3) can be implemented as .
CMOS
However the naive implementation will result in up to 30 transistors. Since , we can defined as and that can be implemented using a single AOI222 which is defined as - i.e. . It can also be implemented using a OAI222 gate the very same way. Since , then
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