From WikiChip
Difference between revisions of "arm holdings/microarchitectures/cortex-a75"
< arm holdings

(fixed)
(→‎Architecture)
Line 72: Line 72:
 
=== Memory Hierarchy ===
 
=== Memory Hierarchy ===
 
{{empty section}}
 
{{empty section}}
 +
 +
== All Cortex-A75 Processors ==
 +
<!-- NOTE:
 +
          This table is generated automatically from the data in the actual articles.
 +
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
          created and tagged accordingly.
 +
 +
          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 +
-->
 +
{{comp table start}}
 +
<table class="comptable sortable tc4 tc6 tc9">
 +
{{comp table header|main|8:List of Cortex-A75-based Processors}}
 +
{{comp table header|main|6:Main processor|2:Integrated Graphics}}
 +
{{comp table header|cols|Family|Launched|Process|Arch|Cores|%Frequency|GPU|%Frequency}}
 +
{{#ask: [[Category:all microprocessor models]] [[microarchitecture::Cortex-A75]]
 +
|?full page name
 +
|?model number
 +
|?family
 +
|?first launched
 +
|?process
 +
|?microarchitecture
 +
|?core count
 +
|?base frequency#GHz
 +
|?integrated gpu
 +
|?integrated gpu base frequency
 +
|format=template
 +
|template=proc table 3
 +
|userparam=10
 +
|mainlabel=-
 +
|valuesep=,
 +
}}
 +
{{comp table count|ask=[[Category:all microprocessor models]] [[microarchitecture::Cortex-A75]]}}
 +
</table>
 +
{{comp table end}}

Revision as of 19:52, 28 March 2025

Edit Values
Cortex-A75 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionMay 29, 2017
Process16 nm, 14 nm, 10 nm, 7 nm
Core Configs1, 2
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages11-13
Decode3-way
Instructions
ISAARMv8.2
ExtensionsFPU, NEON
Cache
L1I Cache8-64 KiB/core
4-way set associative
L1D Cache8-64 KiB/core
4-way set associative
L2 Cache64-256-512 KiB/core
L3 Cache0-4 MiB/Cluster
Succession

Cortex-A75 (codename Prometheus) is the successor to Cortex-A73, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market.

This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A75, which implemented the ARMv8.2 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A55) in a DynamIQ big.LITTLE configuration to achieve better energy/performance.

Compiler support

Compiler Arch-Specific Arch-Favorable
Arm Compiler -mcpu=cortex-a75 -mtune=cortex-a75
GCC -mcpu=cortex-a75 -mtune=cortex-a75
LLVM -mcpu=cortex-a75 -mtune=cortex-a75

If the Cortex-A75 is coupled with the Cortex-A55 in a big.LITTLE system,

GCC also supports the following option:
Compiler Tune
GCC -mtune=cortex-a75.cortex-a55

Architecture

See also: ARM and Cortex

Key changes from Cortex-A73

New text document.svg This section is empty; you can help add the missing info by editing this page.

Block Diagram

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy

New text document.svg This section is empty; you can help add the missing info by editing this page.

All Cortex-A75 Processors

 List of Cortex-A75-based Processors
 Main processorIntegrated Graphics
ModelFamilyLaunchedProcessArchCoresFrequencyGPUFrequency
9820ExynosJanuary 20198 nm
0.008 μm
8.0e-6 mm
Cortex-A75, Cortex-A55, Exynos M48Mali-G76
9825Exynos20197 nm
0.007 μm
7.0e-6 mm
Cortex-A75, Cortex-A55, M482.73 GHz
2,730 MHz
2,730,000 kHz
, 2.4 GHz
2,400 MHz
2,400,000 kHz
, 1.95 GHz
1,950 MHz
1,950,000 kHz
Mali-G76754 MHz
0.754 GHz
754,000 KHz
Helio G80Helio3 February 202012 nm
0.012 μm
1.2e-5 mm
Cortex-A75, Cortex-A5581.8 GHz
1,800 MHz
1,800,000 kHz
, 2 GHz
2,000 MHz
2,000,000 kHz
Mali-G52950 MHz
0.95 GHz
950,000 KHz
P65Helio25 June 201912 nm
0.012 μm
1.2e-5 mm
Cortex-A75, Cortex-A5582 GHz
2,000 MHz
2,000,000 kHz
Mali-G52820 MHz
0.82 GHz
820,000 KHz
P90Helio13 December 201812 nm
0.012 μm
1.2e-5 mm
Cortex-A75, Cortex-A5582.2 GHz
2,200 MHz
2,200,000 kHz
, 2 GHz
2,000 MHz
2,000,000 kHz
PowerVR GM 9446970 MHz
0.97 GHz
970,000 KHz
SDM670Snapdragon 6008 August 201810 nm
0.01 μm
1.0e-5 mm
Cortex-A75, Cortex-A5581.7 GHz
1,700 MHz
1,700,000 kHz
, 2.2 GHz
2,200 MHz
2,200,000 kHz
Adreno 615
SDM710Snapdragon 70023 May 201810 nm
0.01 μm
1.0e-5 mm
Cortex-A75, Cortex-A5582.2 GHz
2,200 MHz
2,200,000 kHz
, 1.7 GHz
1,700 MHz
1,700,000 kHz
Adreno 616500 MHz
0.5 GHz
500,000 KHz
SDM712Snapdragon 7006 February 201910 nm
0.01 μm
1.0e-5 mm
Cortex-A75, Cortex-A5582.3 GHz
2,300 MHz
2,300,000 kHz
, 1.7 GHz
1,700 MHz
1,700,000 kHz
Adreno 616550 MHz
0.55 GHz
550,000 KHz
SDM845Snapdragon 800February 201810 nm
0.01 μm
1.0e-5 mm
Cortex-A75, Cortex-A5582.8 GHz
2,800 MHz
2,800,000 kHz
, 1.7 GHz
1,700 MHz
1,700,000 kHz
Adreno 630 GPU710 MHz
0.71 GHz
710,000 KHz
SDM850Snapdragon 800, Snapdragon 85 June 201810 nm
0.01 μm
1.0e-5 mm
Cortex-A75, Cortex-A5582.96 GHz
2,960 MHz
2,960,000 kHz
, 1.77 GHz
1,770 MHz
1,770,000 kHz
Adreno 630710 MHz
0.71 GHz
710,000 KHz
Count: 10
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/cortex-a75&oldid=103089"
Facts about "Cortex-A75 - Microarchitectures - ARM"
RDF feed
codenameCortex-A75 +
core count1 + and 2 +
designerARM Holdings +
first launchedMay 29, 2017 +
full page namearm holdings/microarchitectures/cortex-a75 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A75 +
pipeline stages (max)13 +
pipeline stages (min)11 +
process16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) +