Latest revision as of 14:41, 3 November 2021

Core i5-12600KF is a 64-bit deca-core high-end performance x86 desktop microprocessor introduced by Intel in late 2021. This processor, which is based on the Alder Lake microarchitecture, is manufactured on Intel's Intel 7 process. The i5-12600KF is a heterogeneous multicore SoC integrating six big Golden Cove cores along with four small Gracemont cores. The big cores operate at 3.7 GHz with a Turbo Boost frequency of up to 4.9 GHz. The small cores operate at 2.8 GHz with a Turbo Boost frequency of up to 3.6 GHz. This processor has a base power of 125 W and a maximum turbo power of 150 W. This chip supports up to 128 GiB of dual-channel DDR5-4800 memory.

The i5-12600K is an identical version of this chip with integrated graphics.

Cache[edit]

Main article: Alder Lake § Cache

This processor features 20 MiB of L3 cache shared among all the big cores and all the small core clusters.

Small Core[edit]

Main article: Gracemont § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 384 KiB 393,216 B 0.375 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 4x64 KiB     L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB     L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     1x2 MiB     L3$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     1x2 MiB

Big Core[edit]

Main article: Golden Cove § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 480 KiB 491,520 B 0.469 MiB L1I$ 192 KiB 196,608 B 0.188 MiB 6x32 KiB     L1D$ 288 KiB 294,912 B 0.281 MiB 6x48 KiB     L2$ 7.5 MiB 7,680 KiB 7,864,320 B 0.00732 GiB     6x1.25 MiB     L3$ 18 MiB 18,432 KiB 18,874,368 B 0.0176 GiB     6x3 MiB

Memory controller[edit]

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR5-4800, DDR4-3200 Supports ECC No Max Mem 128 GiB Controllers 1 Channels 2 Max Bandwidth 71.53 GiB/s 73,246.72 MiB/s 76.805 GB/s 76,804.753 MB/s 0.0699 TiB/s 0.0768 TB/s Bandwidth Single 35.76 GiB/s Double 71.53 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 5.0 Max Lanes: 16 Configuration: 1x16, 2x8 PCIe Revision: 4.0 Max Lanes: 4 Configuration: 1x4

Graphics[edit]

This microprocessor does not have integrated graphics.

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology SST Speed Shift Technology vPro Intel vPro VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) Secure Key Secure Key Technology SMEP OS Guard Technology VMD Volume Management Device MBE Ctrl Mode-Based Execute Control DL Boost Deep Learning Boost

Die[edit]

Main article: Alder Lake § ADL-S (8P+8E) Die

Alder Lake S (C0) microprocessors are fabricated on Intel's Intel 7 process. This SoC uses a single 215.25 mm² monolithic die which includes both the CPU cores along with the integrated GPU and various other additional components.

• Intel 7 process
• 10.5 mm x 20.5 mm
• 215.25 mm² die size

Documents[edit]

• Product Brief