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Difference between revisions of "risc-v/microarchitectures"
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| RV[32,64]IMAFDCV || {{sifive|7 Series|l=arch}} | | RV[32,64]IMAFDCV || {{sifive|7 Series|l=arch}} | ||
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− | | rowspan=" | + | | rowspan="3" | [[T-Head]] || RV64GC[V,RV] || {{t-head|C910}} |
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− | | {{t-head|E902}} || | + | | RV32[EMC,EC,IMC] || {{t-head|E902}} |
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+ | | RV64GC[V] || {{t-head|C906}} | ||
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| rowspan="2" | Universities || RV32IM || [[Vanilla-5]] | | rowspan="2" | Universities || RV32IM || [[Vanilla-5]] |
Latest revision as of 16:07, 13 November 2022
RISC-V
Instruction Set Architecture
Instruction Set Architecture
General
Base Variants(base)
Standard Extensions(all)
Topics
- Foundation
- Non-Standard Extensions
- Addressing Modes
- Registers
- Assembly
- Interrupts
- Microarchitectures
Various microarchitectures have been designed for RISC-V by a number of companies. Below is a list of those microarchitectures.
List of RISC-V microarchitectures[edit]
Designer | ISA | Microarchitectures |
---|---|---|
Andes | RV32IMAC | N25 |
Codasip | RV32[E,I]MC[F] | CODIX-BK3 |
RV[32,64]IMC[F][D] | CODIX-BK5 | |
RV64IMAC, RV64GC | CODIX-BK7 | |
Esperanto | RV64GC | ET-Minion, ET-Maxion |
RV32IMC | BottleRocket | |
Microsemi | RV32IMA/F | Mi-V |
Nvidia | RV64I | NV-RISCV |
SiFive | RV32IMAC | E31 |
RV64IMAC | E51 | |
RV64GC | E54-MC | |
RV[32,64]IMAFDCV | 7 Series | |
T-Head | RV64GC[V,RV] | C910 |
RV32[EMC,EC,IMC] | E902 | |
RV64GC[V] | C906 | |
Universities | RV32IM | Vanilla-5 |
RV32G/RV64G | Rocket |