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{{intel title|Xeon Silver 4215R}}
 
{{intel title|Xeon Silver 4215R}}
−
{{chip}}
+
{{chip
 +
|name=Xeon Silver 4215R
 +
|image=cascade lake sp (front).png
 +
|designer=Intel
 +
|manufacturer=Intel
 +
|model number=4215R
 +
|market=Server
 +
|first announced=February 24, 2020
 +
|first launched=February 24, 2020
 +
|release price (tray)=$794.00
 +
|S-Spec=SRGZE
 +
|family=Xeon Silver
 +
|series=4200
 +
|frequency=3,200 MHz
 +
|turbo frequency1=4,000 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 +
|clock multiplier=32
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Cascade Lake
 +
|platform=Purley
 +
|chipset=Lewisburg
 +
|core name=Cascade Lake R
 +
|core family=6
 +
|process=14 nm
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=8
 +
|thread count=16
 +
|max memory=1 TiB
 +
|max cpus=2
 +
|smp interconnect=UPI
 +
|smp interconnect links=2
 +
|smp interconnect rate=9.6 GT/s
 +
|tdp=130 W
 +
|tcase min=0 °C
 +
|tcase max=79 °C
 +
|package name 1=intel,fclga_3647
 +
|predecessor=Xeon Silver 4215
 +
|predecessor link=intel/xeon silver/4215
 +
}}
 +
'''Xeon Silver 4215R''' is a {{arch|64}} [[8-core]] [[x86]] mid-range performance server microprocessor introduced by [[Intel]] in early [[2020]]. The Silver 4215R is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports dual-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 3.2 GHz with a TDP of 130 W and features a {{intel|turbo boost}} frequency of up to 4.0 GHz.
 +
 
 +
== Cache ==
 +
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
 +
{{cache size
 +
|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=8x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=8x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=8 MiB
 +
|l2 break=8x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=11 MiB
 +
|l3 break=8x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2400
 +
|ecc=Yes
 +
|max mem=1 TiB
 +
|controllers=2
 +
|channels=6
 +
|max bandwidth=107.3 GiB/s
 +
|bandwidth schan=17.88 GiB/s
 +
|bandwidth dchan=35.76 GiB/s
 +
|bandwidth qchan=71.53 GiB/s
 +
|bandwidth hchan=107.3 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=48
 +
|pcie config=1x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 +
}}
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=Yes
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=No
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|intelrunsure=No
 +
|mbe=Yes
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|dlboost=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
}}
 +
 
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=3,200MHz
 +
|freq_1=4,000MHz
 +
|freq_2=4,000MHz
 +
|freq_3=3,800MHz
 +
|freq_4=3,800MHz
 +
|freq_5=3,600MHz
 +
|freq_6=3,600MHz
 +
|freq_7=3,600MHz
 +
|freq_8=3,600MHz
 +
|freq_avx2_base=2,000MHz
 +
|freq_avx2_1=3,600MHz
 +
|freq_avx2_2=3,600MHz
 +
|freq_avx2_3=3,300MHz
 +
|freq_avx2_4=3,300MHz
 +
|freq_avx2_5=2,600MHz
 +
|freq_avx2_6=2,600MHz
 +
|freq_avx2_7=2,600MHz
 +
|freq_avx2_8=2,600MHz
 +
|freq_avx512_base=1,500MHz
 +
|freq_avx512_1=3,300MHz
 +
|freq_avx512_2=3,300MHz
 +
|freq_avx512_3=2,600MHz
 +
|freq_avx512_4=2,600MHz
 +
|freq_avx512_5=2,000MHz
 +
|freq_avx512_6=2,000MHz
 +
|freq_avx512_7=2,000MHz
 +
|freq_avx512_8=2,000MHz
 +
}}

Latest revision as of 18:00, 3 August 2022

Edit Values
Xeon Silver 4215R
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number4215R
MarketServer
IntroductionFebruary 24, 2020 (announced)
February 24, 2020 (launched)
Release Price$794.00 (tray)
ShopAmazon
General Specs
FamilyXeon Silver
Series4200
Frequency3,200 MHz
Turbo Frequency4,000 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier32
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake R
Core Family6
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads16
Max Memory1 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
InterconnectUPI
Interconnect Links2
Interconnect Rate9.6 GT/s
Electrical
TDP130 W
Tcase0 °C – 79 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Silver 4215R is a 64-bit 8-core x86 mid-range performance server microprocessor introduced by Intel in early 2020. The Silver 4215R is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports dual-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 3.2 GHz with a TDP of 130 W and features a turbo boost frequency of up to 4.0 GHz.

Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  8x1 MiB16-way set associativewrite-back
L3$11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
  8x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth107.3 GiB/s
109,875.2 MiB/s
115.212 GB/s
115,212.498 MB/s
0.105 TiB/s
0.115 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: 1x16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
MBE CtrlMode-Based Execute Control
DL BoostDeep Learning Boost

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
12345678
Normal3,200MHz4,000MHz4,000MHz3,800MHz3,800MHz3,600MHz3,600MHz3,600MHz3,600MHz
AVX22,000MHz3,600MHz3,600MHz3,300MHz3,300MHz2,600MHz2,600MHz2,600MHz2,600MHz
AVX5121,500MHz3,300MHz3,300MHz2,600MHz2,600MHz2,000MHz2,000MHz2,000MHz2,000MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_silver/4215r&oldid=100356"
Facts about "Xeon Silver 4215R - Intel"
RDF feed
base frequency3,200 MHz (3.2 GHz, 3,200,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier32 +
core count8 +
core family6 +
core nameCascade Lake SP +
designerIntel +
familyXeon Silver +
first announcedFebruary 24, 2020 +
first launchedFebruary 24, 2020 +
full page nameintel/xeon silver/4215r +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
ldateFebruary 24, 2020 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max case temperature352.15 K (79 °C, 174.2 °F, 633.87 °R) +
max cpu count2 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number4215R +
nameXeon Silver 4215R +
packageFCLGA-3647 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 794.00 (€ 714.60, £ 643.14, ¥ 82,044.02) +
release price (tray)$ 794.00 (€ 714.60, £ 643.14, ¥ 82,044.02) +
series4200 +
smp interconnectUPI +
smp interconnect links2 +
smp interconnect rate9.6 GT/s +
smp max ways2 +
socketSocket P + and LGA-3647 +
tdp130 W (130,000 mW, 0.174 hp, 0.13 kW) +
technologyCMOS +
thread count16 +
turbo frequency (1 core)4,000 MHz (4 GHz, 4,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +