(21 intermediate revisions by 15 users not shown) | |||
Line 9: | Line 9: | ||
|part number=YD1600BBAEBOX | |part number=YD1600BBAEBOX | ||
|part number 2=YD1600BBM6IAE | |part number 2=YD1600BBM6IAE | ||
+ | |part number 3=YD1600BBM6IAF | ||
+ | |part number 4=YD1600BBAFBOX | ||
|market=Desktop | |market=Desktop | ||
|first announced=March 16, 2017 | |first announced=March 16, 2017 | ||
Line 42: | Line 44: | ||
|core count=6 | |core count=6 | ||
|thread count=12 | |thread count=12 | ||
+ | |max memory=64 GiB | ||
|max cpus=1 | |max cpus=1 | ||
− | |||
|tdp=65 W | |tdp=65 W | ||
− | |package | + | |package name 1=amd,socket am4 |
}} | }} | ||
'''Ryzen 5 1600''' is a {{arch|64}} [[hexa-core]] mid-range performance [[x86]] desktop microprocessor introduced by [[AMD]] in early [[2017]]. This processor is based on AMD's {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricated on a [[14 nm process]]. The 1600 operates at a base frequency of 3.2 GHz with a [[TDP]] of 65 W and a {{amd|Precision Boost|Boost}} frequency of up to 3.6 GHz. This model is a less overclockable friendly version of the {{\\|1600X}}. This MPU supports up to 64 GiB of dual-channel DDR4-2666 ECC memory. | '''Ryzen 5 1600''' is a {{arch|64}} [[hexa-core]] mid-range performance [[x86]] desktop microprocessor introduced by [[AMD]] in early [[2017]]. This processor is based on AMD's {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricated on a [[14 nm process]]. The 1600 operates at a base frequency of 3.2 GHz with a [[TDP]] of 65 W and a {{amd|Precision Boost|Boost}} frequency of up to 3.6 GHz. This model is a less overclockable friendly version of the {{\\|1600X}}. This MPU supports up to 64 GiB of dual-channel DDR4-2666 ECC memory. | ||
+ | |||
+ | In December 2019 AMD [https://wccftech.com/first-gen-amd-ryzen-cpus-are-appearing-with-12nm-zen-architecture/ silently launched] a new variant, dubbed Ryzen 5 1600 "AF" (based on the changed SKU). It's based on the newer and improved Zen+ architecture and user testings suggest a slightly higher boost clock (3600Mhz compared to 3300MHz for original "AE") under multi-core load compared to the fresh-man 1600. | ||
== Cache == | == Cache == | ||
{{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}} | {{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}} | ||
{{cache size | {{cache size | ||
− | |l1 cache=576 | + | |l1 cache=576 KiB |
− | |l1i cache=384 | + | |l1i cache=384 KiB |
− | |l1i break=6x64 | + | |l1i break=6x64 KiB |
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
− | |l1d cache=192 | + | |l1d cache=192 KiB |
− | |l1d break=6x32 | + | |l1d break=6x32 KiB |
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l1d policy=write-back | |l1d policy=write-back | ||
− | |l2 cache=3 | + | |l2 cache=3 MiB |
− | |l2 break=6x512 | + | |l2 break=6x512 KiB |
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
|l2 policy=write-back | |l2 policy=write-back | ||
− | |l3 cache=16 | + | |l3 cache=16 MiB |
− | |l3 break=2x8 | + | |l3 break=2x8 MiB |
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
}} | }} | ||
Line 71: | Line 75: | ||
== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=DDR4- | + | |type=DDR4-3600 |
|ecc=Yes | |ecc=Yes | ||
|max mem=64 GiB | |max mem=64 GiB | ||
Line 126: | Line 130: | ||
|sse42=Yes | |sse42=Yes | ||
|sse4a=Yes | |sse4a=Yes | ||
+ | |sse_gfni=No | ||
|avx=Yes | |avx=Yes | ||
+ | |avx_gfni=No | ||
|avx2=Yes | |avx2=Yes | ||
− | + | |avx512f=No | |
+ | |avx512cd=No | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx512vnni=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |avx512gfni=No | ||
+ | |avx512vaes=No | ||
+ | |avx512vbmi2=No | ||
+ | |avx512bitalg=No | ||
+ | |avx512vpclmulqdq=No | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
Line 142: | Line 165: | ||
|clmul=Yes | |clmul=Yes | ||
|f16c=Yes | |f16c=Yes | ||
+ | |bfloat16=No | ||
|tbt1=No | |tbt1=No | ||
|tbt2=No | |tbt2=No | ||
|tbmt3=No | |tbmt3=No | ||
+ | |tvb=No | ||
|bpt=No | |bpt=No | ||
|eist=No | |eist=No | ||
Line 150: | Line 175: | ||
|flex=No | |flex=No | ||
|fastmem=No | |fastmem=No | ||
+ | |ivmd=No | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
|isrt=No | |isrt=No | ||
|sba=No | |sba=No | ||
Line 167: | Line 199: | ||
|securekey=No | |securekey=No | ||
|osguard=No | |osguard=No | ||
+ | |intqat=No | ||
+ | |dlboost=No | ||
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
|smartmp=No | |smartmp=No | ||
|powernow=No | |powernow=No | ||
− | |amdvi= | + | |amdvi=No |
− | |amdv= | + | |amdv=No |
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
|rvi=No | |rvi=No | ||
|smt=Yes | |smt=Yes | ||
|sensemi=Yes | |sensemi=Yes | ||
|xfr=No | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
}} | }} | ||
* This model has partial {{amd|XFR}} support, allowing for an additional +[[amd xfr headroom::100]] MHz boost frequency. | * This model has partial {{amd|XFR}} support, allowing for an additional +[[amd xfr headroom::100]] MHz boost frequency. |
Latest revision as of 05:42, 24 June 2024
Edit Values | |
AMD Ryzen 5 1600 | |
General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Model Number | 1600 |
Part Number | YD1600BBAEBOX, YD1600BBM6IAE, YD1600BBM6IAF, YD1600BBAFBOX |
Market | Desktop |
Introduction | March 16, 2017 (announced) April 11, 2017 (launched) |
Release Price | $219 |
Shop | Amazon |
General Specs | |
Family | Ryzen 5 |
Series | Ryzen |
Locked | No |
Frequency | 3,200 MHz |
Turbo Frequency | Yes |
Turbo Frequency | 3,600 MHz (1 core), 3,600 MHz (2 cores), 3,300 MHz (3 cores), 3,300 MHz (4 cores), 3,300 MHz (5 cores), 3,300 MHz (6 cores) |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 32 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen |
Chipset | Promontory |
Core Name | Summit Ridge |
Core Family | 23 |
Core Model | 1 |
Core Stepping | B1 |
Process | 14 nm |
Transistors | 4,800,000,000 |
Technology | CMOS |
Die | 213 mm² |
Word Size | 64 bit |
Cores | 6 |
Threads | 12 |
Max Memory | 64 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 65 W |
Packaging | |
Package | OPGA-1331 |
Package Type | Organic Micro Pin Grid Array |
Dimension | 40 mm × 40 mm |
Pitch | 1 mm |
Contacts | 1331 |
Socket | Socket AM4 |
Ryzen 5 1600 is a 64-bit hexa-core mid-range performance x86 desktop microprocessor introduced by AMD in early 2017. This processor is based on AMD's Zen microarchitecture and is fabricated on a 14 nm process. The 1600 operates at a base frequency of 3.2 GHz with a TDP of 65 W and a Boost frequency of up to 3.6 GHz. This model is a less overclockable friendly version of the 1600X. This MPU supports up to 64 GiB of dual-channel DDR4-2666 ECC memory.
In December 2019 AMD silently launched a new variant, dubbed Ryzen 5 1600 "AF" (based on the changed SKU). It's based on the newer and improved Zen+ architecture and user testings suggest a slightly higher boost clock (3600Mhz compared to 3300MHz for original "AE") under multi-core load compared to the fresh-man 1600.
Cache[edit]
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller[edit]
Integrated Memory Controller
|
||||||||||||||
|
[Edit] Memory Configurations | |||
---|---|---|---|
Dual Channel | Single Rank | 2 DIMMs | DDR4-2666 |
4 DIMMs | DDR4-2133 | ||
Double Rank | 2 DIMMs | DDR4-2400 | |
4 DIMMs | DDR4-1866 |
Expansions[edit]
The 1600 includes 20 PCIe lanes - 16 for a DGP and 4 for storage (NVMe or 2 ports SATA Express).
Expansion Options
|
||||||||||||||||||||||||||||
|
- eMMC, LPC, SMBus, SPI/eSPI
Audio[edit]
Support Azalia High Definition Audio
Graphics[edit]
This processor has no integrated graphics.
Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
- This model has partial XFR support, allowing for an additional +100100 MHzMHz boost frequency.
0.1 GHz
100,000 kHz
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Ryzen 5 1600 - AMD#io + |
amd xfr headroom | 100 MHz (0.1 GHz, 100,000 kHz) + |
base frequency | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
chipset | Promontory + |
clock multiplier | 32 + |
core count | 6 + |
core family | 23 + |
core model | 1 + |
core name | Summit Ridge + |
core stepping | B1 + |
designer | AMD + |
die area | 213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) + |
family | Ryzen 5 + |
first announced | March 16, 2017 + |
first launched | April 11, 2017 + |
full page name | amd/ryzen 5/1600 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd sensemi technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
has locked clock multiplier | false + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
ldate | 3000 + |
manufacturer | GlobalFoundries + |
market segment | Desktop + |
max cpu count | 1 + |
max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
max memory bandwidth | 39.74 GiB/s (40,693.76 MiB/s, 42.671 GB/s, 42,670.5 MB/s, 0.0388 TiB/s, 0.0427 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 20 + |
microarchitecture | Zen + |
model number | 1600 + |
name | AMD Ryzen 5 1600 + |
package | OPGA-1331 + |
part number | YD1600BBAEBOX +, YD1600BBM6IAE +, YD1600BBM6IAF + and YD1600BBAFBOX + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 219.00 (€ 197.10, £ 177.39, ¥ 22,629.27) + |
series | Ryzen + |
smp max ways | 1 + |
socket | Socket AM4 + |
supported memory type | DDR4-3600 + |
tdp | 65 W (65,000 mW, 0.0872 hp, 0.065 kW) + |
technology | CMOS + |
thread count | 12 + |
transistor count | 4,800,000,000 + |
turbo frequency (1 core) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
turbo frequency (2 cores) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
turbo frequency (3 cores) | 3,300 MHz (3.3 GHz, 3,300,000 kHz) + |
turbo frequency (4 cores) | 3,300 MHz (3.3 GHz, 3,300,000 kHz) + |
turbo frequency (5 cores) | 3,300 MHz (3.3 GHz, 3,300,000 kHz) + |
turbo frequency (6 cores) | 3,300 MHz (3.3 GHz, 3,300,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |