From WikiChip
Difference between revisions of "Talk:amd/cores/picasso"
< Talk:amd

(→‎PCIe lanes)
 
Line 4: Line 4:
 
Is it 12 PCIe lanes (1x8 for GPU + 1x4 for storage) or 20 PCIe lanes (1x16 for GPU + 1x4 for storage) as does individual entries of the series insist? <small><span class="autosigned">—&nbsp;Preceding [[WikiChip:Signatures|unsigned]] comment added by [[User:90.190.182.206|90.190.182.206]] ([[User talk:90.190.182.206|talk]] • [[Special:Contributions/90.190.182.206|contribs]]) </span></small><!-- Template:Unsigned -->
 
Is it 12 PCIe lanes (1x8 for GPU + 1x4 for storage) or 20 PCIe lanes (1x16 for GPU + 1x4 for storage) as does individual entries of the series insist? <small><span class="autosigned">—&nbsp;Preceding [[WikiChip:Signatures|unsigned]] comment added by [[User:90.190.182.206|90.190.182.206]] ([[User talk:90.190.182.206|talk]] • [[Special:Contributions/90.190.182.206|contribs]]) </span></small><!-- Template:Unsigned -->
  
−
It's both, depending on if it's Socket AM4 or Socket FP5. --[[User:David|David]] ([[User talk:David|talk]]) 07:13, 5 August 2019 (EDT)
+
:It's both, depending on if it's Socket AM4 or Socket FP5. --[[User:David|David]] ([[User talk:David|talk]]) 07:13, 5 August 2019 (EDT)

Latest revision as of 06:13, 5 August 2019

This is the discussion page for the amd/cores/picasso page.
  • Please use this page to discuss possible errors, inconsistencies, omissions, changes, and further clarifications regarding the content of amd/cores/picasso.
  • If you are looking for a particular model that's missing, please add its name to this page.

PCIe lanes[edit]

Is it 12 PCIe lanes (1x8 for GPU + 1x4 for storage) or 20 PCIe lanes (1x16 for GPU + 1x4 for storage) as does individual entries of the series insist? — Preceding unsigned comment added by 90.190.182.206 (talk • contribs)

It's both, depending on if it's Socket AM4 or Socket FP5. --David (talk) 07:13, 5 August 2019 (EDT)
Retrieved from "https://en.wikichip.org/w/index.php?title=Talk:amd/cores/picasso&oldid=92836"