From WikiChip
Difference between revisions of "intel/microarchitectures/tremont"
< intel‎ | microarchitectures

m (Reverted edits by 45.33.136.113 (talk) to last revision by 175.143.166.162)
(One-word typo fix. (Accross to across))
 
(17 intermediate revisions by 8 users not shown)
Line 5: Line 5:
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
−
|introduction=2018/2019
+
|introduction=2019
−
|process=14/10 nm
+
|process=10 nm
 
|type=Superscalar
 
|type=Superscalar
 
|oooe=Yes
 
|oooe=Yes
Line 24: Line 24:
 
|extension 11=PCLMUL
 
|extension 11=PCLMUL
 
|extension 12=RDRND
 
|extension 12=RDRND
−
|extension 13=SHA
+
|extension 13=XSAVE
−
|core name=Gemini Lake
+
|extension 14=XSAVEOPT
 +
|extension 15=FSGSBASE
 +
|extension 16=PTWRITE
 +
|extension 17=RDPID
 +
|extension 18=SGX
 +
|extension 19=UMIP
 +
|extension 20=GFNI-SSE
 +
|extension 21=CLWB
 +
|extension 22=ENCLV
 +
|extension 23=SHA
 +
|core name=Elkhart Lake
 +
|core name 2=Jasper Lake
 +
|core name 3=Skyhawk Lake
 +
|core name 4=Lakefield
 +
|core name 5=Snow Ridge
 
|predecessor=Goldmont Plus
 
|predecessor=Goldmont Plus
 
|predecessor link=intel/microarchitectures/goldmont plus
 
|predecessor link=intel/microarchitectures/goldmont plus
Line 31: Line 45:
 
|successor link=intel/microarchitectures/gracemont
 
|successor link=intel/microarchitectures/gracemont
 
}}
 
}}
−
'''Tremont''' is [[Intel]]'s successor to {{\\|Goldmont Plus}}, a [[14 nm]] or [[10 nm]] microarchitecture for ultra-low power devices and microservers.
+
'''Tremont''' is [[Intel]]'s successor to {{\\|Goldmont Plus}}, a [[10 nm]] microarchitecture for ultra-low power devices and microservers.
  
 
== Codenames ==
 
== Codenames ==
 
{| class="wikitable"
 
{| class="wikitable"
−
! Platform !! Core Name
+
! Platform !! Core Name || PCH
 
|-
 
|-
−
| Jacobsville || {{intel|Elkhart Lake|l=core}}?
+
| || {{intel|Skyhawk Lake|l=core}} ||
 +
|-
 +
| Jacobsville || {{intel|Elkhart Lake|l=core}} || {{intel|Mule Creek Canyon|l=chipset}}
 +
|-
 +
| || {{intel|Jasper Lake|l=core}} ||
 +
|-
 +
| || {{intel|Lakefield|l=core}} ||
 +
|-
 +
| || {{intel|Snow Ridge |l=core}} ||
 
|}
 
|}
  
Line 44: Line 66:
  
 
== Release Dates ==
 
== Release Dates ==
−
{{empty section}}
+
Tremont was released in a number of products in late 2019.
  
 
== Technology ==
 
== Technology ==
−
Tremont appear to be planned for Intel's [[10 nm process]].
+
Tremont uses Intel's [[10 nm process]].
  
 
== Compiler support ==
 
== Compiler support ==
Line 54: Line 76:
 
! Compiler !! Arch-Specific || Arch-Favorable
 
! Compiler !! Arch-Specific || Arch-Favorable
 
|-
 
|-
−
| [[ICC]] || <code>-march=?</code> || <code>-mtune=?</code>
+
| [[ICC]] || <code>-march=tremont</code> || <code>-mtune=tremont</code>
 
|-
 
|-
−
| [[GCC]] || <code>-march=?</code> || <code>-mtune=?</code>
+
| [[GCC]] || <code>-march=tremont</code> || <code>-mtune=tremont</code>
 
|-
 
|-
 
| [[LLVM]] || <code>-march=tremont</code> || <code>-mtune=tremont</code>
 
| [[LLVM]] || <code>-march=tremont</code> || <code>-mtune=tremont</code>
Line 73: Line 95:
  
 
== Architecture ==
 
== Architecture ==
−
{{future information}}
+
Tremont is designed with significant single-thread performance in mind while focusing on low-power small silicon area cores.
 
=== Key changes from {{\\|Goldmont Plus}} ===
 
=== Key changes from {{\\|Goldmont Plus}} ===
−
* Graphics
+
* Significant [[IPC]] uplift ([[Intel]] self-reported average 32% IPC across proxy benchmarks such as [[SPEC CPU2006]]/[[SPEC CPU2017]])
−
** {{intel|Gen 11|l=arch}}
+
* Front-end
 +
** Redesigned front-end
 +
*** New dual symmetric decode cluster
 +
**** Out-of-order decode
 +
**** 6-wide decode
 +
***** 3-way decode per cluster
 +
** Smarter [[prefetchers]]
 +
** Improved [[branch predictor]]
 +
*** Big-core level of performance
 +
* Back-end
 +
** larger ROB
 +
** wide issue (10-wide)
 +
* Execution Engine
 +
** 2x store data ports (up from 1)
 +
 
  
 
====New instructions ====
 
====New instructions ====
Line 88: Line 124:
 
* User wait instructions: TPAUSE, UMONITOR, UMWAIT
 
* User wait instructions: TPAUSE, UMONITOR, UMWAIT
 
* Split Lock Detection - detection and cause an exception for split locks
 
* Split Lock Detection - detection and cause an exception for split locks
 +
 +
=== Block Diagram ===
 +
==== Individual Core ====
 +
:[[File:tremont block diagram.svg|850px]]

Latest revision as of 18:12, 10 December 2020

Edit Values
Tremont µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2019
Process10 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, ENCLV, SHA
Cores
Core NamesElkhart Lake,
Jasper Lake,
Skyhawk Lake,
Lakefield,
Snow Ridge
Succession

Tremont is Intel's successor to Goldmont Plus, a 10 nm microarchitecture for ultra-low power devices and microservers.

Codenames[edit]

Platform Core Name PCH
Skyhawk Lake
Jacobsville Elkhart Lake Mule Creek Canyon
Jasper Lake
Lakefield
Snow Ridge

Brands[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Release Dates[edit]

Tremont was released in a number of products in late 2019.

Technology[edit]

Tremont uses Intel's 10 nm process.

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
ICC -march=tremont -mtune=tremont
GCC -march=tremont -mtune=tremont
LLVM -march=tremont -mtune=tremont
Visual Studio /arch:? /tune:?

CPUID[edit]

Core Extended
Family 		Family Extended
Model 		Model
 ? 0 0x6 0x8 0x6
Family 6 Model 134

Architecture[edit]

Tremont is designed with significant single-thread performance in mind while focusing on low-power small silicon area cores.

Key changes from Goldmont Plus[edit]

  • Significant IPC uplift (Intel self-reported average 32% IPC across proxy benchmarks such as SPEC CPU2006/SPEC CPU2017)
  • Front-end
    • Redesigned front-end
      • New dual symmetric decode cluster
        • Out-of-order decode
        • 6-wide decode
          • 3-way decode per cluster
    • Smarter prefetchers
    • Improved branch predictor
      • Big-core level of performance
  • Back-end
    • larger ROB
    • wide issue (10-wide)
  • Execution Engine
    • 2x store data ports (up from 1)


New instructions[edit]

Tremont introduced a number of new instructions:

  • CLWB - Force cache line write-back without flush
  • ENCLV - SGX oversubscription instructions
  • CLDEMOTE - Cache line demote instruction
  • SSE_GFNI - SSE-based Galois Field New Instructions
  • Direct store instructions: MOVDIRI, MOVDIR64B
  • User wait instructions: TPAUSE, UMONITOR, UMWAIT
  • Split Lock Detection - detection and cause an exception for split locks

Block Diagram[edit]

Individual Core[edit]

tremont block diagram.svg
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/tremont&oldid=98268"
Facts about "Tremont - Microarchitectures - Intel"
RDF feed
codenameTremont +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/tremont +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameTremont +
process10 nm (0.01 μm, 1.0e-5 mm) +