From WikiChip
Difference between revisions of "ibm/power/02cy415"
< ibm

m (Reverted edits by 141.95.54.180 (talk) to last revision by David)
 
(3 intermediate revisions by 2 users not shown)
Line 36: Line 36:
 
}}
 
}}
 
'''POWER9 02CY415''' is a [[20-core]] [[POWER]] server and workstation microprocessor designed by [[IBM]] and introduced in late [[2017]]. This chip is based on the {{ibm|POWER9|l=arch}} microarchitecture and is fabricated on GlobalFoundries [[14 nm process|14nm SOI Process]]. The 02CY415 has a base frequency of 2.40 GHz with a bost frequency of 3.80 GHz and a TDP of 160 W.
 
'''POWER9 02CY415''' is a [[20-core]] [[POWER]] server and workstation microprocessor designed by [[IBM]] and introduced in late [[2017]]. This chip is based on the {{ibm|POWER9|l=arch}} microarchitecture and is fabricated on GlobalFoundries [[14 nm process|14nm SOI Process]]. The 02CY415 has a base frequency of 2.40 GHz with a bost frequency of 3.80 GHz and a TDP of 160 W.
 +
 +
== Cache ==
 +
{{main|ibm/microarchitectures/power9#Memory_Hierarchy|l1=POWER9 § Cache}}
 +
{{cache size
 +
|l1 cache=1.25 MiB
 +
|l1i cache=640 KiB
 +
|l1i break=20x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=640 KiB
 +
|l1d break=20x32 KiB
 +
|l1d desc=8-way set associative
 +
|l2 cache=5 MiB
 +
|l2 break=10x512 KiB
 +
|l2 desc=8-way set associative
 +
|l3 cache=100 MiB
 +
|l3 break=10x10 MiB
 +
|l3 desc=20-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2666
 +
|ecc=No
 +
|max mem=2 TiB
 +
|controllers=2
 +
|channels=8
 +
|max bandwidth=158.95 GiB/s
 +
|bandwidth schan=19.87 GiB/s
 +
|bandwidth dchan=39.74 GiB/s
 +
|bandwidth qchan=79.47 GiB/s
 +
|bandwidth ochan=158.95 GiB/s
 +
}}
 +
 +
{{ibm power9 sforza memory configs}}
 +
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=4.0
 +
|pcie lanes=48
 +
|pcie config=x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 +
}}
 +
 +
== Die ==
 +
{{see also|ibm/microarchitectures/power9#Die|l1=POWER9 § Die}}
 +
A die shot of IBM's [[22-core]] server microprocessor used in this part:
 +
 +
: [[File:power9 so die.png|500px]]
 +
 +
 +
: [[File:power9 so die (annotated).png|500px]]

Latest revision as of 15:25, 18 September 2022

Edit Values
02CY415
General Info
DesignerIBM
ManufacturerGlobalFoundries
Model Number02CY415
Part Number02CY415
MarketServer, Workstation
IntroductionNovember, 2017 (announced)
November, 2017 (launched)
General Specs
FamilyPOWER
SeriesPOWER9
Frequency2.40 GHz
Turbo Frequency3.80 GHz
Microarchitecture
ISAPower ISA v3.0B (Power ISA)
MicroarchitecturePOWER9
Core NameSforza
Process14 nm
Transistors8,000,000,000
TechnologyCMOS
Die693.37 mm²
25.228 mm × 27.48416 mm
Word Size64 bit
Cores20
Threads80
Max Memory2 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
TDP160 W
Tjunction0 °C – 85 °C
Packaging
PackageFCLGA-2601 (PLGA)
Dimension50 mm × 50 mm
Pitch1.016 mm
Contacts2601

POWER9 02CY415 is a 20-core POWER server and workstation microprocessor designed by IBM and introduced in late 2017. This chip is based on the POWER9 microarchitecture and is fabricated on GlobalFoundries 14nm SOI Process. The 02CY415 has a base frequency of 2.40 GHz with a bost frequency of 3.80 GHz and a TDP of 160 W.

Cache[edit]

Main article: POWER9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.25 MiB
1,280 KiB
1,310,720 B
L1I$640 KiB
655,360 B
0.625 MiB
20x32 KiB8-way set associative 
L1D$640 KiB
655,360 B
0.625 MiB
20x32 KiB8-way set associative 
L2$5 MiB
5,120 KiB
5,242,880 B
0.00488 GiB
  10x512 KiB8-way set associative 
L3$100 MiB
102,400 KiB
104,857,600 B
0.0977 GiB
  10x10 MiB20-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCNo
Max Mem2 TiB
Controllers2
Channels8
Max Bandwidth158.95 GiB/s
162,764.8 MiB/s
170.671 GB/s
170,671.263 MB/s
0.155 TiB/s
0.171 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Octa 158.95 GiB/s
[Edit] Memory Configurations
Configuration Speed
One DIMM per channel 2666 MHz
Two DIMMs per channel 2400 MHz

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 4.0
Max Lanes: 48
Configuration: x16, x8, x4


Die[edit]

See also: POWER9 § Die

A die shot of IBM's 22-core server microprocessor used in this part:

power9 so die.png


power9 so die (annotated).png
Retrieved from "https://en.wikichip.org/w/index.php?title=ibm/power/02cy415&oldid=100523"
Facts about "POWER9 02CY415 - IBM"
RDF feed
full page nameibm/power/02cy415 +
instance ofmicroprocessor +
ldate1900 +