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Difference between revisions of "samsung/microarchitectures/m2"
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{{samsung title|Mongoose 2 (M2)|arch}}
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{{samsung title|Exynos M2|arch}}
 
{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
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|speculative=Yes
 
|speculative=Yes
 
|renaming=Yes
 
|renaming=Yes
 +
|stages=14
 
|decode=4-way
 
|decode=4-way
 
|isa=ARMv8
 
|isa=ARMv8
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|successor link=samsung/microarchitectures/m3
 
|successor link=samsung/microarchitectures/m3
 
}}
 
}}
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'''Mongoose 2''' ('''M2''') is an [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics serving as a successor to the {{\\|Mongoose 1}}.
+
'''Exynos Mongoose 2''' ('''M2''') is the successor to the {{\\|Mongoose 1}}, a [[10 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics.
  
 
== Process Technology ==
 
== Process Technology ==
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! Compiler !! Arch-Specific || Arch-Favorable
 
! Compiler !! Arch-Specific || Arch-Favorable
 
|-
 
|-
−
| [[GCC]] || <code>-mcpu=exynos-m2</code> || <code>-mtune=exynos-m2</code>
+
| [[GCC]] || <code>-mcpu=exynos-m1</code> || <code>-mtune=exynos-m1</code>
 
|-
 
|-
 
| [[LLVM]] || <code>-mcpu=exynos-m2</code> || <code>-mtune=exynos-m2</code>
 
| [[LLVM]] || <code>-mcpu=exynos-m2</code> || <code>-mtune=exynos-m2</code>
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== Architecture ==
 
== Architecture ==
 
=== Key changes from {{\\|Mongoose 1}} ===
 
=== Key changes from {{\\|Mongoose 1}} ===
−
* [[10 nm|10nm 10LPE process]] (from [[14 nm]])
+
* [[10 nm|10nm (10LPE) process]] (from [[14 nm]])
 +
* Larger [[ROB]] (100, up from 96)
 
{{expand list}}
 
{{expand list}}
  
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==== Individual Core ====
 
==== Individual Core ====
−
<small>(Core identical to {{\\|Mongoose 1}})</small>
+
[[File:mongoose 2 block diagram.svg|900px]]
−
 
 
−
[[File:mongoose 1 block diagram.svg|900px]]
 
  
 
=== Memory Hierarchy ===
 
=== Memory Hierarchy ===
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*** 16 B/cycle/CPU bandwidth
 
*** 16 B/cycle/CPU bandwidth
  
−
Mongoose 1 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
+
The M2 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
  
 
* TLBs
 
* TLBs
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** 64-entry µBTB
 
** 64-entry µBTB
 
** 64-entry return stack
 
** 64-entry return stack
 +
** 8K-entry L2 BTB
  
 
== Core ==
 
== Core ==
−
The M2 core appears to be fairly identical to the {{\\|Mongoose 1|M1}}.
+
The M2 core is almost identical to the {{\\|M1}}.
  
 
== All M2 Processors ==
 
== All M2 Processors ==

Latest revision as of 13:50, 21 February 2019

Edit Values
Mongoose 2 µarch
General Info
Arch TypeCPU
DesignerSamsung
ManufacturerSamsung
IntroductionFebruary 23, 2017
Phase-out2018
Process10 nm
Core Configs4
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14
Decode4-way
Instructions
ISAARMv8
Cache
L1I Cache64 KiB/core
4-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache2 MiB/cluster
16-way set associative
Succession

Exynos Mongoose 2 (M2) is the successor to the Mongoose 1, a 10 nm ARM microarchitecture designed by Samsung for their consumer electronics.

Process Technology[edit]

M2 was fabricated on Samsung's first generation 10LPE (Low Power Early) process.

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
GCC -mcpu=exynos-m1 -mtune=exynos-m1
LLVM -mcpu=exynos-m2 -mtune=exynos-m2

Architecture[edit]

Key changes from Mongoose 1[edit]

This list is incomplete; you can help by expanding it.

Block Diagram[edit]

Core Cluster Overview[edit]

(Cluster identical to Mongoose 1)

mongoose 1 soc block diagram.svg

Individual Core[edit]

mongoose 2 block diagram.svg

Memory Hierarchy[edit]

  • Cache
    • L1I Cache
      • 64 KiB, 4-way set associative
        • 128 B line size
        • per core
      • Parity-protected
    • L1D Cache
      • 32 KiB, 8-way set associative
        • 64 B line size
        • per core
      • 4 cycles for fastest load-to-use
      • 16 B/cycle load bandwidth
      • 16 B/cycle store bandwidth
    • L2 Cache
      • 2 MiB, 16-way set associative
        • 4x banks (512 KiB each)
      • Inclusive of L1
      • 22 cycles latency
      • 16 B/cycle/CPU bandwidth

The M2 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

  • TLBs
    • ITLB
      • 256-entry
    • DTLB
      • 32-entry
    • STLB
      • 1,024-entry
      • Per core
  • BPU
    • 4K-entry main BTB
    • 64-entry µBTB
    • 64-entry return stack
    • 8K-entry L2 BTB

Core[edit]

The M2 core is almost identical to the M1.

All M2 Processors[edit]

 List of M2-based Processors
 Main processorIntegrated Graphics
ModelFamilyLaunchedArchCoresFrequencyTurboGPUFrequency
Count: 0
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Facts about "Exynos M2 - Microarchitectures - Samsung"
RDF feed
codenameMongoose 2 +
core count4 +
designerSamsung +
first launchedFebruary 23, 2017 +
full page namesamsung/microarchitectures/m2 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerSamsung +
microarchitecture typeCPU +
nameMongoose 2 +
phase-out2018 +
pipeline stages14 +
process10 nm (0.01 μm, 1.0e-5 mm) +