From WikiChip
Difference between revisions of "arm holdings/microarchitectures/cortex-a72"
< arm holdings

(→‎Architecture)
m (typo)
 
(7 intermediate revisions by 3 users not shown)
Line 6: Line 6:
 
|manufacturer=TSMC
 
|manufacturer=TSMC
 
|introduction=April 23, 2015
 
|introduction=April 23, 2015
 +
|isa=ARMv8
 
|predecessor=Cortex-A57
 
|predecessor=Cortex-A57
 
|predecessor link=arm_holdings/microarchitectures/cortex-a57
 
|predecessor link=arm_holdings/microarchitectures/cortex-a57
Line 11: Line 12:
 
|successor link=arm_holdings/microarchitectures/cortex-a73
 
|successor link=arm_holdings/microarchitectures/cortex-a73
 
}}
 
}}
−
'''Cortex-A72''' (codename '''Maya''') is the successor to the {{armh|Cortex-A57|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A72, which implemented the {{arm|ARMv8}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A53}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance.
+
'''Cortex-A72''' (codename '''Maia''') is the successor to the {{armh|Cortex-A57|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A72, which implemented the {{arm|ARMv8}} ISA, is a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A53}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance.
 +
 
 +
== Compiler support ==
 +
{| class="wikitable"
 +
|-
 +
! Compiler !! Arch-Specific || Arch-Favorable
 +
|-
 +
| [[Arm Compiler]] || <code>-mcpu=cortex-a72</code> || <code>-mtune=cortex-a72</code>
 +
|-
 +
| [[GCC]] || <code>-mcpu=cortex-a72</code> || <code>-mtune=cortex-a72</code>
 +
|-
 +
| [[LLVM]] || <code>-mcpu=cortex-a72</code> || <code>-mtune=cortex-a72</code>
 +
|}
 +
 
 +
If the Cortex-A72 is coupled with the {{\\|Cortex-A53}} or the {{\\|Cortex-A35}} in a [[big.LITTLE]] system, GCC also supports the following option:
 +
 
 +
{| class="wikitable"
 +
|-
 +
! Compiler !! Tune
 +
|-
 +
| [[GCC]] || <code>-mtune=cortex-a72.cortex-a53</code><br><code>-mtune=cortex-a72.cortex-a35</code>
 +
|}
  
 
== Architecture ==
 
== Architecture ==
Line 38: Line 60:
  
 
:[[File:mt6797 die.png|600px]]
 
:[[File:mt6797 die.png|600px]]
 +
 +
== Bibliography ==
 +
* Mair, Hugh T., et al. "4.3 A 20nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.

Latest revision as of 14:57, 4 July 2022

Edit Values
Cortex-A72 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionApril 23, 2015
Instructions
ISAARMv8
Succession

Cortex-A72 (codename Maia) is the successor to the Cortex-A57, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A72, which implemented the ARMv8 ISA, is a performant core which is often combined with a number of lower power cores (e.g. Cortex-A53) in a big.LITTLE configuration to achieve better energy/performance.

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
Arm Compiler -mcpu=cortex-a72 -mtune=cortex-a72
GCC -mcpu=cortex-a72 -mtune=cortex-a72
LLVM -mcpu=cortex-a72 -mtune=cortex-a72

If the Cortex-A72 is coupled with the Cortex-A53 or the Cortex-A35 in a big.LITTLE system, GCC also supports the following option:

Compiler Tune
GCC -mtune=cortex-a72.cortex-a53
-mtune=cortex-a72.cortex-a35

Architecture[edit]

Key changes from Cortex-A57[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Block Diagram[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Die[edit]

MediaTek Helio X20[edit]

  • TSMC 20 nm process
  • 100 mm² die size
  • Quad-core ULP Cortex-A53
    • ~21.81 mm² per cluster
      • ~4.23 mm² per core
  • Quad-core efficient Cortex-A53
    • ~29.73 mm² per cluster
      • ~5.41 mm² per core
  • Dual-core High-performance Cortex-A72 + 1 MiB L2
    • ~27.36 mm² per cluster
      • ~ 9.60 mm² per core
      • ~ 7.50 mm² for 1 MiB L2


mt6797 die.png

Bibliography[edit]

  • Mair, Hugh T., et al. "4.3 A 20nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/cortex-a72&oldid=100288"
Facts about "Cortex-A72 - Microarchitectures - ARM"
RDF feed
codenameCortex-A72 +
designerARM Holdings +
first launchedApril 23, 2015 +
full page namearm holdings/microarchitectures/cortex-a72 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A72 +