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Difference between revisions of "x86/persistent memory extensions"
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| <code>CLFLUSHOPT</code> || Optimized CLFLUSH; Behaves similarly to <code>CLFLUSH</code> but without the serialization, thereby optimized for performance by allowing for some concurrency when executing multiple CLFLUSHOPT instructions back-to-back.
 
| <code>CLFLUSHOPT</code> || Optimized CLFLUSH; Behaves similarly to <code>CLFLUSH</code> but without the serialization, thereby optimized for performance by allowing for some concurrency when executing multiple CLFLUSHOPT instructions back-to-back.
 
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|-
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| <code>CLWB</code> || Cache line write back; behaves similarly to <code>CLFLUSHOPT</code> but keeps the cache line valid (i.e., the cache line is flushed and then marked as no longer dirty) thereby optimized for performance by keeping the line in the cache, increasing the cache of a [[cache hit]].
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| <code>CLWB</code> || Cache line write back; behaves similarly to <code>CLFLUSHOPT</code> but keeps the cache line valid (i.e., the cache line is flushed and then marked as no longer dirty) thereby optimized for performance by keeping the line in the cache, increasing the chance of a [[cache hit]].
 
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|}
  
 
Both of the new instructions must follow by a <code>SFENCE</code> to ensure all flushes are completed before continuing.
 
Both of the new instructions must follow by a <code>SFENCE</code> to ensure all flushes are completed before continuing.
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== Detection ==
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{| class="wikitable"
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! colspan="2" | {{x86|CPUID}} !! rowspan="2" | Instruction Set
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|-
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! Input !! Output
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|-
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| rowspan="2" | EAX=07H, ECX=0 || EBX[bit 23] || CLFLUSHOPT
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|-
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| EBX[bit 24] || CLWB
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|}
  
 
== Microarchitecture support ==
 
== Microarchitecture support ==
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== See also ==
 
== See also ==
 
* {{snia|NVM Programming Model}}
 
* {{snia|NVM Programming Model}}
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[[Category:x86_extensions]]

Latest revision as of 19:08, 13 May 2021

x86
Instruction Set Architecture
General
Variants
Topics
CPUIDs
Modes
Extensions(all)
v · d · e

Persistent memory extensions (PMEM) are a set of x86 instructions designed to improve the usability of working with storage-class memory.

Overview[edit]

Intel adopted the SNIA NVM Programming Model for working with persistent memory. This model allows for direct access (DAX) using byte-addressable operations (i.e., load/store), however, the persistence of the data in the cache is not guaranteed until it has entered the persistence domain. x86 provides a set of instructions for flushing cache lines in a more optimized way. In addition to existing x86 instructions such as non-temporal stores, CLFLUSH, and WBINVD (kernel only), two new instructions were added:

Instruction Description
CLFLUSHOPT Optimized CLFLUSH; Behaves similarly to CLFLUSH but without the serialization, thereby optimized for performance by allowing for some concurrency when executing multiple CLFLUSHOPT instructions back-to-back.
CLWB Cache line write back; behaves similarly to CLFLUSHOPT but keeps the cache line valid (i.e., the cache line is flushed and then marked as no longer dirty) thereby optimized for performance by keeping the line in the cache, increasing the chance of a cache hit.

Both of the new instructions must follow by a SFENCE to ensure all flushes are completed before continuing.

Detection[edit]

CPUID Instruction Set
Input Output
EAX=07H, ECX=0 EBX[bit 23] CLFLUSHOPT
EBX[bit 24] CLWB

Microarchitecture support[edit]

Instruction Introduction
Intel AMD
CLFLUSHOPT Skylake (server)
Skylake (client)
Goldmont 		Zen
CLWB Skylake (server)
Ice Lake (client) 		Zen 2

Intrinsic functions[edit]

#include <immintrin.h>

# clflushopt
void _mm_clflushopt (void const * p)

# clwb
void _mm_clwb (void const * p)

See also[edit]

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