Semiconductor & Computer Engineering
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Difference between revisions of "hisilicon/kunpeng/hi1610"
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{{cache size | {{cache size | ||
|l1 cache=1.25 MiB | |l1 cache=1.25 MiB | ||
| − | |l1i cache=768 | + | |l1i cache=768 KiB |
|l1i break=16x48 KiB | |l1i break=16x48 KiB | ||
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
Latest revision as of 02:03, 17 July 2019
| Edit Values | |
| Hi1610 | |
| General Info | |
| Designer | HiSilicon, ARM Holdings |
| Manufacturer | TSMC |
| Model Number | Hi1610 |
| Market | Server |
| Introduction | 2015 (announced) 2015 (launched) |
| General Specs | |
| Family | Hi16xx |
| Frequency | 2,100 MHz |
| Microarchitecture | |
| ISA | ARMv8 (ARM) |
| Microarchitecture | Cortex-A57 |
| Core Name | Cortex-A57 |
| Process | 16 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 16 |
| Threads | 16 |
| Max Memory | 128 GiB |
| Multiprocessing | |
| Max SMP | 2-Way (Multiprocessor) |
Hi1610 is a hexadeca-core 64-bit ARM server microprocessor introduced by HiSilicon in late 2015. Fabricated by TSMC on a 16 nm process, this chip incorporates 16 Cortex-A57 cores operating at 2.1 GHz. The Hi1610 supports up to 128 GiB of dual-channel DDR4-1866 memory.
Cache[edit]
- Main article: Cortex-A57 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
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Supported ARM Extensions & Processor Features
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Utilizing devices[edit]
- HiSilicon D02
This list is incomplete; you can help by expanding it.
Facts about "Hi1610 - HiSilicon"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Hi1610 - HiSilicon#pcie + |
| base frequency | 2,100 MHz (2.1 GHz, 2,100,000 kHz) + |
| core count | 16 + |
| core name | Cortex-A57 + |
| designer | HiSilicon + and ARM Holdings + |
| family | Hi16xx + |
| first announced | 2015 + |
| first launched | 2015 + |
| full page name | hisilicon/kunpeng/hi1610 + |
| has ecc memory support | true + |
| instance of | microprocessor + |
| isa | ARMv8 + |
| isa family | ARM + |
| l1$ size | 1,280 KiB (1,310,720 B, 1.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 786,432 KiB (805,306,368 B, 768 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
| ldate | 2015 + |
| manufacturer | TSMC + |
| market segment | Server + |
| max cpu count | 2 + |
| max memory | 131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) + |
| max memory bandwidth | 55.63 GiB/s (56,965.12 MiB/s, 59.732 GB/s, 59,732.258 MB/s, 0.0543 TiB/s, 0.0597 TB/s) + |
| max memory channels | 2 + |
| microarchitecture | Cortex-A57 + |
| model number | Hi1610 + |
| name | Hi1610 + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + |
| smp max ways | 2 + |
| supported memory type | DDR4-1866 + |
| technology | CMOS + |
| thread count | 16 + |
| used by | HiSilicon D02 + |
| word size | 64 bit (8 octets, 16 nibbles) + |