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Difference between revisions of "apm/x-gene/apm883208-x1"
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|thread count=8
 
|thread count=8
 
|max memory=256 GiB
 
|max memory=256 GiB
 +
|v core=0.9 V
 +
|v io=1.8 V
 +
|v io 2=2.5 V
 +
|v io 3=3.3 V
 +
|tdp=45 W
 +
|tjunc min=0 °C
 +
|tjunc max=90 °C
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|successor=APM883208-X2
 +
|successor link=apm/x-gene/apm883208-x2
 
}}
 
}}
 
'''APM883208-X1''' is a {{arch|64}} [[octa-core]] [[ARM]] server microprocessor designed by [[AppliedMicro]] and introduced in [[2012]]. Fabricated on [[TSMC]] [[40 nm process]] based on the {{apm|Storm|l=arch}} microarchitecture, this processor has eight custom [[ARMv8]] cores operating at up to 2.4 GHz and supporting up to 256 GiB of dual-channel DDR3-1866 memory.
 
'''APM883208-X1''' is a {{arch|64}} [[octa-core]] [[ARM]] server microprocessor designed by [[AppliedMicro]] and introduced in [[2012]]. Fabricated on [[TSMC]] [[40 nm process]] based on the {{apm|Storm|l=arch}} microarchitecture, this processor has eight custom [[ARMv8]] cores operating at up to 2.4 GHz and supporting up to 256 GiB of dual-channel DDR3-1866 memory.
 +
 +
== Cache ==
 +
{{main|apm/microarchitectures/storm#Memory_Hierarchy|l1=Storm § Cache}}
 +
{{cache size
 +
|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=8x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=8x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=Write-through with write-combine
 +
|l2 cache=1 MiB
 +
|l2 break=4x256 KiB
 +
|l3 cache=8 MiB
 +
|l3 break=1x8 MiB
 +
}}
 +
 +
== Memory controller ==
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{{memory controller
 +
|type=DDR3-1866
 +
|ecc=Yes
 +
|max mem=256 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=27.82 GiB/s
 +
|bandwidth schan=13.91 GiB/s
 +
|bandwidth dchan=27.82 GiB/sP
 +
}}
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 +
== Expansions ==
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{{expansions main
 +
|
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{{expansions entry
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|type=PCIe
 +
|pcie revision=3.0
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|pcie lanes=17
 +
|pcie config=1x16+x1
 +
|pcie config 2=2x8+x1
 +
}}
 +
{{expansions entry
 +
|type=USB
 +
|usb revision=2.0
 +
|usb ports=2
 +
}}
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{{expansions entry
 +
|type=SATA
 +
|sata revision=3.0
 +
|sata ports=6
 +
}}
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}}
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* 2x I2C
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* 4x UARTs
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* GPIOs
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* 2x SPI
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* 2x SDIO 3.0
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* JTAG / Trace
 +
 +
=== Network ===
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{{network
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|mii opts=Yes
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|rgmii=Yes
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|rgmii ports=4
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|sgmii=Yes
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|sgmii ports=1
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}}
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 +
* Note: some ports are muxed
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== Block diagram ==
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:[[File:208-x1-block.png|800px]]
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== Documents ==
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* [[:File:208-X1_PB.pdf|Product Brief]]
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* Eval kits
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** [[:File:208-x1-pro-1-x-gene-x-c1-evaluation-kit-product-brief.pdf|APM883208-X1 X-Gene X-C1 Evaluation Kit]]
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** [[:File:208-x-gene-x-c1-evaluation-kit-product-brief1.pdf|APM883208-X1 X-Gene X-C1 Evaluation Kit]]
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** [[:File:208-x1-pru-1-x-gene-x-c1-evaluation-kit-product-brief.pdf|APM883208-X1 X-Gene X-C1 Evaluation Kit]]

Latest revision as of 01:10, 26 September 2018

Edit Values
APM883208-X1
General Info
DesignerAppliedMicro
ManufacturerTSMC
Model NumberAPM883208-X1
MarketServer
IntroductionOctober 28, 2011 (announced)
2012 (launched)
General Specs
FamilyX-Gene
SeriesX-Gene 1
Turbo Frequency2,400 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureStorm
Core NamePotenza
Process40 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Max Memory256 GiB
Electrical
Vcore0.9 V
VI/O1.8 V, 2.5 V, 3.3 V
TDP45 W
Tjunction0 °C – 90 °C
Succession

APM883208-X1 is a 64-bit octa-core ARM server microprocessor designed by AppliedMicro and introduced in 2012. Fabricated on TSMC 40 nm process based on the Storm microarchitecture, this processor has eight custom ARMv8 cores operating at up to 2.4 GHz and supporting up to 256 GiB of dual-channel DDR3-1866 memory.

Cache[edit]

Main article: Storm § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativeWrite-through with write-combine
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB  
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  1x8 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1866
Supports ECCYes
Max Mem256 GiB
Controllers1
Channels2
Max Bandwidth27.82 GiB/s
28,487.68 MiB/s
29.871 GB/s
29,871.498 MB/s
0.0272 TiB/s
0.0299 TB/s
Bandwidth
Single 13.91 GiB/s
Double 27.82 GiB/sP

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 17
Configuration: 1x16+x1, 2x8+x1
USBRevision: 2.0
Max Ports: 2
SATARevision: 3.0
Max Ports: 6
  • 2x I2C
  • 4x UARTs
  • GPIOs
  • 2x SPI
  • 2x SDIO 3.0
  • JTAG / Trace

Network[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 4)
SGMIIYes (Ports: 1)
  • Note: some ports are muxed

Block diagram[edit]

208-x1-block.png

Documents[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=apm/x-gene/apm883208-x1&oldid=82863"
Facts about "X-Gene 1 APM883208-X1 - AppliedMicro"
RDF feed
core count8 +
core namePotenza +
designerAppliedMicro +
familyX-Gene +
first announcedOctober 28, 2011 +
first launched2012 +
full page nameapm/x-gene/apm883208-x1 +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
ldate2012 +
manufacturerTSMC +
market segmentServer +
max memory262,144 MiB (268,435,456 KiB, 274,877,906,944 B, 256 GiB, 0.25 TiB) +
microarchitectureStorm +
model numberAPM883208-X1 +
nameAPM883208-X1 +
process40 nm (0.04 μm, 4.0e-5 mm) +
seriesX-Gene 1 +
technologyCMOS +
thread count8 +
turbo frequency2,400 MHz (2.4 GHz, 2,400,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +