Semiconductor & Computer Engineering
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{{title|Nodelet}} | {{title|Nodelet}} | ||
| − | '''Nodelets''' are enhanced versions of mature [[technology nodes]] that either improve the power or performance while introducing | + | '''Nodelets''' are enhanced versions of mature [[technology nodes]] that either improve the power or performance while minimizing the overall design rework required, typically without introducing more major changes such as [[optical shrinks]]. Since nodelets rely on existing and proven technologies, those process optimizations do not negatively impact [[yield]] and other reliability aspects of the process. |
== Overview == | == Overview == | ||
| − | Nodelets are a more simplified version of a [[half node]] where either little or no shrink takes place and the emphasis shifts to process optimizations such as improving the [[on resistance|R<sub>on</sub>]]. An example of nodelets include [[12 nm]], [[11 nm]], and [[8 nm]]. | + | Nodelets are a more simplified version of a [[half node]] where either little or no shrink takes place and the emphasis shifts to process optimizations such as improving the [[on resistance|R<sub>on</sub>]] and the [[stray capacitance]]. Sometimes manufacturers will introduce a density improvement through [[standard cell]] changes such as [[track reduction]] or improve the device performance through the relaxation of the [[gate pitch]]. An example of recent nodelets include [[12 nm]], [[11 nm]], and [[8 nm]]. |
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Latest revision as of 19:10, 19 July 2018
Nodelets are enhanced versions of mature technology nodes that either improve the power or performance while minimizing the overall design rework required, typically without introducing more major changes such as optical shrinks. Since nodelets rely on existing and proven technologies, those process optimizations do not negatively impact yield and other reliability aspects of the process.
Overview[edit]
Nodelets are a more simplified version of a half node where either little or no shrink takes place and the emphasis shifts to process optimizations such as improving the Ron and the stray capacitance. Sometimes manufacturers will introduce a density improvement through standard cell changes such as track reduction or improve the device performance through the relaxation of the gate pitch. An example of recent nodelets include 12 nm, 11 nm, and 8 nm.
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