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|frequency 3=2,100 MHz
 
|frequency 3=2,100 MHz
 
|frequency 4=2,200 MHz
 
|frequency 4=2,200 MHz
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|frequency 5=2,300 MHz
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|frequency 6=2,400 MHz
 
|isa=ARMv8.1
 
|isa=ARMv8.1
 
|isa family=ARM
 
|isa family=ARM
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}}
 
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'''ThunderX2 CN9975''' is a {{arch|64}} [[octacosa-core]] high-performance [[ARM]] server microprocessor introduced by [[Cavium]] in mid-[[2018]]. The microprocessor, which is based on the {{cavium|Vulcan|l=arch}} microarchitecture, is fabricated on [[TSMC]]'s [[16 nm process]]. Depending on the exact SKU, the CN9975 operates between 1.8 GHz and 2.4 GHz and supports up to hexa/octa-channel DDR4-2666 memory.
 
'''ThunderX2 CN9975''' is a {{arch|64}} [[octacosa-core]] high-performance [[ARM]] server microprocessor introduced by [[Cavium]] in mid-[[2018]]. The microprocessor, which is based on the {{cavium|Vulcan|l=arch}} microarchitecture, is fabricated on [[TSMC]]'s [[16 nm process]]. Depending on the exact SKU, the CN9975 operates between 1.8 GHz and 2.4 GHz and supports up to hexa/octa-channel DDR4-2666 memory.
 +
 +
== Cache ==
 +
{{main|cavium/microarchitectures/vulcan#Memory_Hierarchy|l1=Vulcan § Cache}}
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{{cache size
 +
|l1 cache=1.75 MiB
 +
|l1i cache=896 KiB
 +
|l1i break=28x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=896 KiB
 +
|l1d break=28x32 KiB
 +
|l1d desc=8-way set associative
 +
|l2 cache=7 MiB
 +
|l2 break=28x256 KiB
 +
|l2 desc=8-way set associative
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|l3 cache=28 MiB
 +
|l3 break=28x1 MiB
 +
}}
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 +
== Memory controller ==
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{{memory controller
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|type=DDR4-2666
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|ecc=Yes
 +
|max mem=2 TiB
 +
|controllers=2
 +
|channels=8
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|max bandwidth=158.95 GiB/s
 +
|bandwidth schan=19.87 GiB/s
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|bandwidth dchan=39.74 GiB/s
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|bandwidth qchan=79.47 GiB/s
 +
|bandwidth hchan=119.21 GiB/s
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|bandwidth ochan=158.95 GiB/s
 +
}}
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 +
== Expansions ==
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{{expansions main
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|
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{{expansions entry
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|type=PCIe
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|pcie revision=3.0
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|pcie lanes=56
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|pcie config=x16
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|pcie config 2=x8
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|pcie config 3=x4
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|pcie config 4=x1
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}}
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{{expansions entry
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|type=SATA
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|sata revision=3
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|sata ports=2
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}}
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{{expansions entry
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|type=USB
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|usb revision=3
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|usb ports=2
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}}
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}}
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== Features ==
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{{arm features
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|thumb=No
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|thumb2=No
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|thumbee=No
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|vfpv1=No
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|vfpv2=No
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|vfpv3=No
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|vfpv3-d16=No
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|vfpv3-f16=No
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|vfpv4=No
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|vfpv4-d16=No
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|vfpv5=No
 +
|neon=Yes
 +
|trustzone=Yes
 +
|jazelle=No
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|wmmx=No
 +
|wmmx2=No
 +
|pmuv3=Yes
 +
|crc32=Yes
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|crypto=Yes
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|fp=Yes
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|fp16=No
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|profile=No
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|ras=No
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|simd=Yes
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|rdm=No
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}}
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 +
== See also ==
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* {{sc|Astra}} supercomputer

Latest revision as of 14:16, 7 May 2019

Edit Values
ThunderX2 CN9975
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN9975
Part NumberCN9975-2400LG4077-Y21-G,
CN9975-2300LG4077-Y21-G,
CN9975-2200LG4077-Y21-G,
CN9975-2100LG4077-Y21-G,
CN9975-2000LG4077-Y21-G,
CN9975-1800LG4077-Y21-G
MarketServer
IntroductionMay 7, 2018 (announced)
May 7, 2018 (launched)
General Specs
FamilyThunderX2
Frequency1,800 MHz, 2,000 MHz, 2,100 MHz, 2,200 MHz, 2,300 MHz, 2,400 MHz
Microarchitecture
ISAARMv8.1 (ARM)
MicroarchitectureVulcan
Process16 nm
TechnologyCMOS
Word Size64 bit
Cores28
Threads112
Max Memory2 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Packaging
PackageFCLGA-4077 (LGA)
Contacts4077

ThunderX2 CN9975 is a 64-bit octacosa-core high-performance ARM server microprocessor introduced by Cavium in mid-2018. The microprocessor, which is based on the Vulcan microarchitecture, is fabricated on TSMC's 16 nm process. Depending on the exact SKU, the CN9975 operates between 1.8 GHz and 2.4 GHz and supports up to hexa/octa-channel DDR4-2666 memory.

Cache[edit]

Main article: Vulcan § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.75 MiB
1,792 KiB
1,835,008 B
L1I$896 KiB
917,504 B
0.875 MiB
28x32 KiB8-way set associative 
L1D$896 KiB
917,504 B
0.875 MiB
28x32 KiB8-way set associative 
L2$7 MiB
7,168 KiB
7,340,032 B
0.00684 GiB
  28x256 KiB8-way set associative 
L3$28 MiB
28,672 KiB
29,360,128 B
0.0273 GiB
  28x1 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem2 TiB
Controllers2
Channels8
Max Bandwidth158.95 GiB/s
162,764.8 MiB/s
170.671 GB/s
170,671.263 MB/s
0.155 TiB/s
0.171 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Octa 158.95 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 56
Configuration: x16, x8, x4, x1
SATARevision: 3
Max Ports: 2
USBRevision: 3
Max Ports: 2


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
TrustZoneTrustZone Security Extensions
PMUv3ARMv8 PMUv3 Performance Monitors Extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FPFloating-point Extension
SIMDAdvanced SIMD extension

See also[edit]

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