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Difference between revisions of "cavium/thunderx2/cn9978"
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{{cavium title|ThunderX2 CN9978}} | {{cavium title|ThunderX2 CN9978}} | ||
− | {{chip}} | + | {{chip |
+ | |name=ThunderX2 CN9978 | ||
+ | |no image=Yes | ||
+ | |designer=Cavium | ||
+ | |manufacturer=TSMC | ||
+ | |model number=CN9978 | ||
+ | |part number=CN9978-2300LG4077-Y21-G | ||
+ | |part number 2=CN9978-2200LG4077-Y21-G | ||
+ | |part number 3=CN9978-2100LG4077-Y21-G | ||
+ | |part number 4=CN9978-2000LG4077-Y21-G | ||
+ | |part number 5=CN9978-1800LG4077-Y21-G | ||
+ | |market=Server | ||
+ | |first announced=May 7, 2018 | ||
+ | |first launched=May 7, 2018 | ||
+ | |family=ThunderX2 | ||
+ | |frequency=1,800 MHz | ||
+ | |frequency 2=2,000 MHz | ||
+ | |frequency 3=2,100 MHz | ||
+ | |frequency 4=2,200 MHz | ||
+ | |frequency 5=2,300 MHz | ||
+ | |isa=ARMv8.1 | ||
+ | |isa family=ARM | ||
+ | |microarch=Vulcan | ||
+ | |process=16 nm | ||
+ | |technology=CMOS | ||
+ | |word size=64 bit | ||
+ | |core count=30 | ||
+ | |thread count=120 | ||
+ | |max cpus=2 | ||
+ | |max memory=2 TiB | ||
+ | |package name 1=cavium,fclga_4077 | ||
+ | }} | ||
'''ThunderX2 CN9978''' is a {{arch|64}} [[triaconta-core]] high-performance [[ARM]] server microprocessor introduced by [[Cavium]] in mid-[[2018]]. The microprocessor, which is based on the {{cavium|Vulcan|l=arch}} microarchitecture, is fabricated on [[TSMC]]'s [[16 nm process]]. Depending on the exact SKU, the CN9978 operates between 1.8 GHz and 2.3 GHz and supports up to quad/octa-channel DDR4-2666 memory. | '''ThunderX2 CN9978''' is a {{arch|64}} [[triaconta-core]] high-performance [[ARM]] server microprocessor introduced by [[Cavium]] in mid-[[2018]]. The microprocessor, which is based on the {{cavium|Vulcan|l=arch}} microarchitecture, is fabricated on [[TSMC]]'s [[16 nm process]]. Depending on the exact SKU, the CN9978 operates between 1.8 GHz and 2.3 GHz and supports up to quad/octa-channel DDR4-2666 memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|cavium/microarchitectures/vulcan#Memory_Hierarchy|l1=Vulcan § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=1.87 MiB | ||
+ | |l1i cache=960 KiB | ||
+ | |l1i break=30x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=960 KiB | ||
+ | |l1d break=30x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l2 cache=7.5 MiB | ||
+ | |l2 break=30x256 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l3 cache=30 MiB | ||
+ | |l3 break=30x1 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=Yes | ||
+ | |max mem=2 TiB | ||
+ | |controllers=2 | ||
+ | |channels=8 | ||
+ | |max bandwidth=158.95 GiB/s | ||
+ | |bandwidth schan=19.87 GiB/s | ||
+ | |bandwidth dchan=39.74 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth hchan=119.21 GiB/s | ||
+ | |bandwidth ochan=158.95 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=56 | ||
+ | |pcie config=x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | |pcie config 4=x1 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=SATA | ||
+ | |sata revision=3 | ||
+ | |sata ports=2 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=USB | ||
+ | |usb revision=3 | ||
+ | |usb ports=2 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{arm features | ||
+ | |thumb=No | ||
+ | |thumb2=No | ||
+ | |thumbee=No | ||
+ | |vfpv1=No | ||
+ | |vfpv2=No | ||
+ | |vfpv3=No | ||
+ | |vfpv3-d16=No | ||
+ | |vfpv3-f16=No | ||
+ | |vfpv4=No | ||
+ | |vfpv4-d16=No | ||
+ | |vfpv5=No | ||
+ | |neon=Yes | ||
+ | |trustzone=Yes | ||
+ | |jazelle=No | ||
+ | |wmmx=No | ||
+ | |wmmx2=No | ||
+ | |pmuv3=Yes | ||
+ | |crc32=Yes | ||
+ | |crypto=Yes | ||
+ | |fp=Yes | ||
+ | |fp16=No | ||
+ | |profile=No | ||
+ | |ras=No | ||
+ | |simd=Yes | ||
+ | |rdm=No | ||
+ | }} |
Latest revision as of 23:15, 3 December 2018
Edit Values | |
ThunderX2 CN9978 | |
General Info | |
Designer | Cavium |
Manufacturer | TSMC |
Model Number | CN9978 |
Part Number | CN9978-2300LG4077-Y21-G, CN9978-2200LG4077-Y21-G, CN9978-2100LG4077-Y21-G, CN9978-2000LG4077-Y21-G, CN9978-1800LG4077-Y21-G |
Market | Server |
Introduction | May 7, 2018 (announced) May 7, 2018 (launched) |
General Specs | |
Family | ThunderX2 |
Frequency | 1,800 MHz, 2,000 MHz, 2,100 MHz, 2,200 MHz, 2,300 MHz |
Microarchitecture | |
ISA | ARMv8.1 (ARM) |
Microarchitecture | Vulcan |
Process | 16 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 30 |
Threads | 120 |
Max Memory | 2 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Packaging | |
Package | FCLGA-4077 (LGA) |
Contacts | 4077 |
ThunderX2 CN9978 is a 64-bit triaconta-core high-performance ARM server microprocessor introduced by Cavium in mid-2018. The microprocessor, which is based on the Vulcan microarchitecture, is fabricated on TSMC's 16 nm process. Depending on the exact SKU, the CN9978 operates between 1.8 GHz and 2.3 GHz and supports up to quad/octa-channel DDR4-2666 memory.
Contents
Cache[edit]
- Main article: Vulcan § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
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Supported ARM Extensions & Processor Features
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Facts about "ThunderX2 CN9978 - Cavium"
full page name | cavium/thunderx2/cn9978 + |
instance of | microprocessor + |
ldate | 1900 + |