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Difference between revisions of "amd/epyc/7551"
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'''EPYC 7551''' is a dual-socket {{arch|64}} [[32-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7551 has a base frequency of 2 GHz with a turbo frequency of 3 GHz for up to 12 active cores. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket. | '''EPYC 7551''' is a dual-socket {{arch|64}} [[32-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7551 has a base frequency of 2 GHz with a turbo frequency of 3 GHz for up to 12 active cores. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket. |
Latest revision as of 12:30, 18 March 2023
Edit Values | |
EPYC 7551 | |
General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Model Number | 7551 |
Part Number | PS7551BDVIHAF |
Market | Server |
Introduction | June 20, 2017 (announced) June 20, 2017 (launched) |
Release Price | $3,400 |
Shop | Amazon |
General Specs | |
Family | EPYC |
Series | 7001 |
Locked | No |
Frequency | 2,000 MHz |
Turbo Frequency | 3,000 MHz (1 core), 3,000 MHz (2 cores), 3,000 MHz (3 cores), 3,000 MHz (4 cores), 3,000 MHz (5 cores), 3,000 MHz (6 cores), 3,000 MHz (7 cores), 3,000 MHz (8 cores), 3,000 MHz (9 cores), 3,000 MHz (10 cores), 3,000 MHz (11 cores), 3,000 MHz (12 cores), 2,550 MHz (13 cores), 2,550 MHz (14 cores), 2,550 MHz (15 cores), 2,550 MHz (16 cores), 2,550 MHz (17 cores), 2,550 MHz (18 cores), 2,550 MHz (19 cores), 2,550 MHz (20 cores), 2,550 MHz (21 cores), 2,550 MHz (22 cores), 2,550 MHz (23 cores), 2,550 MHz (24 cores), 2,550 MHz (25 cores), 2,550 MHz (26 cores), 2,550 MHz (27 cores), 2,550 MHz (28 cores), 2,550 MHz (29 cores), 2,550 MHz (30 cores), 2,550 MHz (31 cores), 2,550 MHz (32 cores) |
Clock multiplier | 20 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen |
Core Name | Naples |
Core Family | 23 |
Core Model | 1 |
Core Stepping | B2 |
Process | 14 nm |
Transistors | 19,200,000,000 |
Technology | CMOS |
Die | 213 mm² |
MCP | Yes (4 dies) |
Word Size | 64 bit |
Cores | 32 |
Threads | 64 |
Max Memory | 2 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
TDP | 180 W |
Tcase | 0 °C – 81 °C |
Packaging | |
Package | SP3, FCLGA-4094 (FC-OLGA) |
Dimension | 75.4 mm × 58.5 mm × 6.26 mm |
Pitch | 0.87 mm × 1 mm |
Contacts | 4094 |
Socket | SP3, LGA-4094 |
EPYC 7551 is a dual-socket 64-bit 32-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7551 has a base frequency of 2 GHz with a turbo frequency of 3 GHz for up to 12 active cores. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket.
Contents
Cache[edit]
- Main article: Zen § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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In a dual-socket configuration, the maximum supported memory doubles to 4 TiB along with the maximum theoretical bandwidth of 317.9 GiB/s.
Expansions[edit]
The EPYC 7551 has 128 Gen 3 PCIe lanes.
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Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
Facts about "EPYC 7551 - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC 7551 - AMD#io + |
base frequency | 2,000 MHz (2 GHz, 2,000,000 kHz) + |
clock multiplier | 20 + |
core count | 32 + |
core family | 23 + |
core model | 1 + |
core name | Naples + |
core stepping | B2 + |
designer | AMD + |
die area | 213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) + |
die count | 4 + |
family | EPYC + |
first announced | June 20, 2017 + |
first launched | June 20, 2017 + |
full page name | amd/epyc/7551 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd secure encrypted virtualization technology | true + |
has amd secure memory encryption technology | true + |
has amd sensemi technology | true + |
has amd transparent secure memory encryption technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
has locked clock multiplier | false + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 3,072 KiB (3,145,728 B, 3 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 2,048 KiB (2,097,152 B, 2 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
ldate | June 20, 2017 + |
manufacturer | GlobalFoundries + |
market segment | Server + |
max case temperature | 354.15 K (81 °C, 177.8 °F, 637.47 °R) + |
max cpu count | 2 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
max memory bandwidth | 158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) + |
max memory channels | 8 + |
max pcie lanes | 128 + |
microarchitecture | Zen + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 7551 + |
name | EPYC 7551 + |
package | SP3 + and FCLGA-4094 + |
part number | PS7551BDVIHAF + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 3,400.00 (€ 3,060.00, £ 2,754.00, ¥ 351,322.00) + |
series | 7001 + |
smp max ways | 2 + |
socket | SP3 + and LGA-4094 + |
supported memory type | DDR4-2666 + |
tdp | 180 W (180,000 mW, 0.241 hp, 0.18 kW) + |
technology | CMOS + |
thread count | 64 + |
transistor count | 19,200,000,000 + |
turbo frequency (10 cores) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
turbo frequency (11 cores) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
turbo frequency (12 cores) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
turbo frequency (13 cores) | 2,550 MHz (2.55 GHz, 2,550,000 kHz) + |
turbo frequency (14 cores) | 2,550 MHz (2.55 GHz, 2,550,000 kHz) + |
turbo frequency (15 cores) | 2,550 MHz (2.55 GHz, 2,550,000 kHz) + |
turbo frequency (16 cores) | 2,550 MHz (2.55 GHz, 2,550,000 kHz) + |
turbo frequency (17 cores) | 2,550 MHz + |
turbo frequency (18 cores) | 2,550 MHz + |
turbo frequency (19 cores) | 2,550 MHz + |
turbo frequency (1 core) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
turbo frequency (20 cores) | 2,550 MHz + |
turbo frequency (21 cores) | 2,550 MHz + |
turbo frequency (22 cores) | 2,550 MHz + |
turbo frequency (23 cores) | 2,550 MHz + |
turbo frequency (24 cores) | 2,550 MHz + |
turbo frequency (25 cores) | 2,550 MHz + |
turbo frequency (26 cores) | 2,550 MHz + |
turbo frequency (27 cores) | 2,550 MHz + |
turbo frequency (28 cores) | 2,550 MHz + |
turbo frequency (29 cores) | 2,550 MHz + |
turbo frequency (2 cores) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
turbo frequency (30 cores) | 2,550 MHz + |
turbo frequency (31 cores) | 2,550 MHz + |
turbo frequency (32 cores) | 2,550 MHz + |
turbo frequency (3 cores) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
turbo frequency (4 cores) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
turbo frequency (5 cores) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
turbo frequency (6 cores) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
turbo frequency (7 cores) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
turbo frequency (8 cores) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
turbo frequency (9 cores) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |