Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/microarchitectures/knights mill"
(→Architecture) |
(→New instructions) |
||
| (3 intermediate revisions by 2 users not shown) | |||
| Line 6: | Line 6: | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|introduction=December 18, 2017 | |introduction=December 18, 2017 | ||
| + | |phase-out=August 9, 2019 | ||
|process=14 nm | |process=14 nm | ||
|type=Superscalar | |type=Superscalar | ||
| Line 21: | Line 22: | ||
|contemporary link=intel/microarchitectures/knights_landing | |contemporary link=intel/microarchitectures/knights_landing | ||
}} | }} | ||
| − | '''Knights Mill''' ('''KNM''') is a special variant of {{\\|Knights Landing}}, a [[14 nm]] [[many-core]] microarchitecture for | + | '''Knights Mill''' ('''KNM''') is a special variant of {{\\|Knights Landing}}, a [[14 nm]] [[many-core]] microarchitecture designed by [[intel]] for high performance computing designed specifically for the [[acceleration]] of artificial intelligence workloads. |
== Brands == | == Brands == | ||
| Line 44: | Line 45: | ||
Knights Mill introduced a number of {{x86|extensions|new instructions}}: | Knights Mill introduced a number of {{x86|extensions|new instructions}}: | ||
| − | * {{x86| | + | * {{x86|AVX512_4FMAPS|<code>AVX5124FMAPS</code>}} - AVX-512 Fused Multiply Accumulation Packed Single precision |
| − | * {{x86| | + | * {{x86|AVX512_4VNNIW|<code>AVX5124VNNIW</code>}} - AVX-512 Vector Neural Network |
| − | * {{x86| | + | * {{x86|AVX512_VPOPCNTDQ|<code>AVX512VPOPCNTDQ</code>}} - AVX-512 Vector Population Count Doubleword and Quadword |
== Memory Hierarchy == | == Memory Hierarchy == | ||
| Line 79: | Line 80: | ||
{{comp table header|main|9:List of Knights Mill-based Processors}} | {{comp table header|main|9:List of Knights Mill-based Processors}} | ||
{{comp table header|main|9:Main processor}} | {{comp table header|main|9:Main processor}} | ||
| − | {{comp table header|cols|Launched|Price|Family|Cores|Threads|L2$|TDP|Base| | + | {{comp table header|cols|Launched|Price|Family|Cores|Threads|L2$|TDP|Base|Turbo}} |
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Knights Mill]] | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Knights Mill]] | ||
|?full page name | |?full page name | ||
Latest revision as of 13:10, 11 November 2024
| Edit Values | |
| Knights Mill µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | December 18, 2017 |
| Phase-out | August 9, 2019 |
| Process | 14 nm |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-16, x86-32, x86-64 |
| Succession | |
| Contemporary | |
| Knights Landing | |
Knights Mill (KNM) is a special variant of Knights Landing, a 14 nm many-core microarchitecture designed by intel for high performance computing designed specifically for the acceleration of artificial intelligence workloads.
Contents
Brands[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Release Dates[edit]
Knights Mill-based processors were introduced in December 2017.
Process Technology[edit]
- See also: Broadwell § Process Technology and 14 nm lithography process
Knights Mill is fabricated on Intel's 14 nm process.
Compiler support[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Architecture[edit]
Key changes from Knights Landing[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
New instructions[edit]
Knights Mill introduced a number of new instructions:
-
AVX5124FMAPS- AVX-512 Fused Multiply Accumulation Packed Single precision -
AVX5124VNNIW- AVX-512 Vector Neural Network -
AVX512VPOPCNTDQ- AVX-512 Vector Population Count Doubleword and Quadword
Memory Hierarchy[edit]
- L1I Cache
- 32 KiB, 8-way set associative
- Per core
- L1D Cache
- 32 KiB, 8-way set associative
- Per core
- L2 Cache
- 1 MiB, 16-way set associative
- Per duplex tile
This list is incomplete; you can help by expanding it.
Overview[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Socket[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
All Knights Mill Chips[edit]
| List of Knights Mill-based Processors | |||||||||
|---|---|---|---|---|---|---|---|---|---|
| Main processor | |||||||||
| Model | Launched | Price | Family | Cores | Threads | L2$ | TDP | Base | Turbo |
| 7235 | 18 December 2017 | Xeon Phi | 64 | 256 | 32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB | 250 W 250,000 mW 0.335 hp 0.25 kW | 1.3 GHz 1,300 MHz 1,300,000 kHz | 1.4 GHz 1,400 MHz 1,400,000 kHz | |
| 7285 | 18 December 2017 | Xeon Phi | 68 | 272 | 34 MiB 34,816 KiB 35,651,584 B 0.0332 GiB | 250 W 250,000 mW 0.335 hp 0.25 kW | 1.3 GHz 1,300 MHz 1,300,000 kHz | 1.4 GHz 1,400 MHz 1,400,000 kHz | |
| 7295 | 18 December 2017 | Xeon Phi | 72 | 288 | 36 MiB 36,864 KiB 37,748,736 B 0.0352 GiB | 320 W 320,000 mW 0.429 hp 0.32 kW | 1.5 GHz 1,500 MHz 1,500,000 kHz | 1.6 GHz 1,600 MHz 1,600,000 kHz | |
| Count: 3 | |||||||||
Facts about "Knights Mill - Microarchitectures - Intel"
| codename | Knights Mill + |
| designer | Intel + |
| first launched | December 18, 2017 + |
| full page name | intel/microarchitectures/knights mill + |
| instance of | microarchitecture + |
| instruction set architecture | x86-16 +, x86-32 + and x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Knights Mill + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |