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=== 3000 Series (Zen) ===
 
=== 3000 Series (Zen) ===
 
{{see also|amd/cores/snowy_owl|amd/microarchitectures/zen|l1=Snowy Owl|l2=Zen µarch}}
 
{{see also|amd/cores/snowy_owl|amd/microarchitectures/zen|l1=Snowy Owl|l2=Zen µarch}}
−
Introduced in early 2018, the 300 embedded series is based on the {{amd|Zen|Zen microarchitecture|l=arch}} using the same dies as the server {{amd|EPYC}} processors. 3000-series come in anywhere from [[4 cores|4]] to [[16 cores]] as well as with and without [[SMT]] support. Models with 8 or less cores come in a single-die configuration and uses a single-chip module {{amd|Package SP4r4}} while models with more than eight cores come in a dual-die configuration and use a multi-chip module {{amd|Package SP4}}. Both packages are ball grid arrays (BGAs) and are pin-compatible with each other. Geared toward embedded applications means those parts have lower TDP than their server counterparts. Depending on the die configuration, the features of the dual-die config are mostly double that of the single-die config.
+
Introduced in early 2018, the 3000 embedded series is based on the {{amd|Zen|Zen microarchitecture|l=arch}} using the same dies as the server {{amd|EPYC}} processors. 3000-series come in anywhere from [[4 cores|4]] to [[16 cores]] as well as with and without [[SMT]] support. Models with 8 or less cores come in a single-die configuration and uses a single-chip module {{amd|Package SP4r4}} while models with more than eight cores come in a dual-die configuration and use a multi-chip module {{amd|Package SP4}}. Both packages are ball grid arrays (BGAs) and are pin-compatible with each other. Geared toward embedded applications means those parts have lower TDP than their server counterparts. Depending on the die configuration, the features of the dual-die config are mostly double that of the single-die config.
  
 
* Dual-die Models
 
* Dual-die Models
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** '''Mem:''' Dual-channel 64-bit DDR4-2666/2133 w/ ECC, up to 512 GiB
 
** '''Mem:''' Dual-channel 64-bit DDR4-2666/2133 w/ ECC, up to 512 GiB
 
** '''I/O:''' x32 PCIe lanes MUX'ed with SATA/GbE and can be mixed configured PCIe and up to 8 SATA ports and up to 4 x 10GbE  ports
 
** '''I/O:''' x32 PCIe lanes MUX'ed with SATA/GbE and can be mixed configured PCIe and up to 8 SATA ports and up to 4 x 10GbE  ports
−
** '''TDP:''' 35-50 W
+
** '''TDP:''' 30-50 W
  
 
The ISA and Technology applies to all models.
 
The ISA and Technology applies to all models.

Latest revision as of 14:06, 25 May 2019

AMD EPYC Embedded
epyc embedded logo.png
EPYC Embedded logo
Developer AMD
Manufacturer GlobalFoundries
Type System on chips
Introduction February 22, 2018 (announced)
February 22, 2018 (launch)
Architecture Embedded x86 SoCs
ISA x86-64
µarch Zen
Word size 64 bit
8 octets
16 nibbles
Process 14 nm
0.014 μm
1.4e-5 mm
Technology CMOS
Clock 1,500 MHz-2,700 MHz
Socket Socket SP4, Socket SP4r2
Succession
←
Opteron

EPYC Embedded is a family of 64-bit multi-core x86 embedded microprocessors designed and introduced by AMD. Those processors are primarily aimed at networking, storage, and edge computing devices. EPYC Embedded effectively succeeded the Opteron A1100 series of embedded microprocessors (although those were actually based on ARM, not x86).

Overview[edit]

The EPYC Embedded family is a low-power variant of the EPYC line that primarily marketed towards embedded devices such as networking, storage, and edge computing devices. Those parts have lower TDPs and come in a much smaller package allowing for denser integration.

Members[edit]

3000 Series (Zen)[edit]

See also: Snowy Owl and Zen µarch

Introduced in early 2018, the 3000 embedded series is based on the Zen microarchitecture using the same dies as the server EPYC processors. 3000-series come in anywhere from 4 to 16 cores as well as with and without SMT support. Models with 8 or less cores come in a single-die configuration and uses a single-chip module Package SP4r4 while models with more than eight cores come in a dual-die configuration and use a multi-chip module Package SP4. Both packages are ball grid arrays (BGAs) and are pin-compatible with each other. Geared toward embedded applications means those parts have lower TDP than their server counterparts. Depending on the die configuration, the features of the dual-die config are mostly double that of the single-die config.

  • Dual-die Models
    • Mem: Quad-channel 64-bit DDR4-2666 w/ ECC, up to 1 TiB
    • I/O: x64 PCIe lanes MUX'ed with SATA/GbE and can be mixed configured PCIe and up to 16 SATA ports and up to 10 x 10GbE ports
    • TDP: 65-100 W
  • Single-die Models
    • Mem: Dual-channel 64-bit DDR4-2666/2133 w/ ECC, up to 512 GiB
    • I/O: x32 PCIe lanes MUX'ed with SATA/GbE and can be mixed configured PCIe and up to 8 SATA ports and up to 4 x 10GbE ports
    • TDP: 30-50 W

The ISA and Technology applies to all models.

 List EPYC Embedded 3000-Series Processors
ModelPriceLaunchedCoresThreadL2$L3$TDPBaseTurbo (Max)MemoryPCIe Lanes
 Single-Chip Package (1 die)
310121 February 2018442 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
35 W
35,000 mW
0.0469 hp
0.035 kW
2.1 GHz
2,100 MHz
2,100,000 kHz
2.9 GHz
2,900 MHz
2,900,000 kHz
DDR4-2666
315121 February 2018482 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
45 W
45,000 mW
0.0603 hp
0.045 kW
2.7 GHz
2,700 MHz
2,700,000 kHz
2.9 GHz
2,900 MHz
2,900,000 kHz
DDR4-2666
320121 February 2018884 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
30 W
30,000 mW
0.0402 hp
0.03 kW
1.5 GHz
1,500 MHz
1,500,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
DDR4-2133
3251$ 315.00
€ 283.50
£ 255.15
¥ 32,548.95
21 February 20188164 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
55 W
55,000 mW
0.0738 hp
0.055 kW
2.5 GHz
2,500 MHz
2,500,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
DDR4-2666
32558164 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
55 W
55,000 mW
0.0738 hp
0.055 kW
2.5 GHz
2,500 MHz
2,500,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
DDR4-2666
 Multi-Chip Package (2 dies)
3301$ 450.00
€ 405.00
£ 364.50
¥ 46,498.50
21 February 201812126 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
65 W
65,000 mW
0.0872 hp
0.065 kW
2 GHz
2,000 MHz
2,000,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
DDR4-2666
335121 February 201812246 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
80 W
80,000 mW
0.107 hp
0.08 kW
1.9 GHz
1,900 MHz
1,900,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
DDR4-2666
340121 February 201816168 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
85 W
85,000 mW
0.114 hp
0.085 kW
1.85 GHz
1,850 MHz
1,850,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
DDR4-2666
3451$ 880.00
€ 792.00
£ 712.80
¥ 90,930.40
21 February 201816328 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
100 W
100,000 mW
0.134 hp
0.1 kW
2.15 GHz
2,150 MHz
2,150,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
DDR4-2666
Count: 9

Documents[edit]

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc_embedded&oldid=91119"
Facts about "EPYC Embedded - AMD"
RDF feed
designerAMD +
first announcedFebruary 22, 2018 +
first launchedFebruary 22, 2018 +
full page nameamd/epyc embedded +
instance ofsystem on a chip family +
instruction set architecturex86-64 +
main designerAMD +
manufacturerGlobalFoundries +
microarchitectureZen +
nameAMD EPYC Embedded +
process14 nm (0.014 μm, 1.4e-5 mm) +
socketSocket SP4 + and Socket SP4r2 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +