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|l1d policy=write-back
 
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|l2 cache=4 MiB
 
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|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 policy=write-back
 
|l2 policy=write-back

Latest revision as of 02:22, 1 January 2018

Edit Values
Celeron N4100
gemini lake (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberN4100
Part NumberFH8068003067408
S-SpecSR3S0
MarketMobile
IntroductionDecember 11, 2017 (announced)
December 11, 2017 (launched)
Release Price$107.00
ShopAmazon
General Specs
FamilyCeleron
Series4000
LockedYes
Frequency1,100 MHz
Turbo Frequency2,400 MHz (1 core)
Clock multiplier11
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureGoldmont Plus
Core NameGemini Lake
Core SteppingB0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads4
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
SDP4.8 W
TDP6 W
Packaging
PackageFCBGA-1090 (BGA)
Dimension25 mm x 24 mm
Contacts1090

Celeron N4100 is a quad-core 64-bit x86 mobile microprocessor introduced by Intel in 2017. This processor is based on Goldmont Plus microarchitecture and is manufactured on a 14 nm process. The N4100 operates at 1.1 GHz and a burst frequency of 2.4 GHz with a TDP of 6 W and an SDP of 4.8 W. This MPU incorporates Intel's UHD Graphics 600 GPU operating at 200 MHz with a burst frequency of 700 MHz.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache[edit]

Main article: Goldmont Plus § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$96 KiB
98,304 B
0.0938 MiB
4x24 KiB6-way set associativewrite-back
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  1x4 MiB16-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCNo
Max Mem8 GiB
Controllers1
Channels2
Max Bandwidth35.76 GiB/s
36,618.24 MiB/s
38.397 GB/s
38,397.008 MB/s
0.0349 TiB/s
0.0384 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 2.0
Max Lanes: 6
Configuration: 1x4+1x2, 4x1, 2x1+1x2+1x2


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUUHD Graphics 600
DesignerIntelDevice ID0x3185
Execution Units12Max Displays3
Max Memory8 GiB
8,192 MiB
8,388,608 KiB
8,589,934,592 B
Frequency200 MHz
0.2 GHz
200,000 KHz
Burst Frequency700 MHz
0.7 GHz
700,000 KHz
OutputDP, eDP, HDMI, DSI
Max Resolution
HDMI4096x2304 @60 Hz
DP4096x2304 @60 Hz
eDP4096x2304 @60 Hz
Standards
DirectX12
OpenGL4.4
OpenCL2.0
DP1.2
eDP1.4
HDMI2.0

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
EISTEnhanced SpeedStep Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
SGXSoftware Guard Extensions
ISRTSmart Response Technology
IPTIdentity Protection Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/n4100&oldid=71862"
Facts about "Celeron N4100 - Intel"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Celeron N4100 - Intel#package + and Celeron N4100 - Intel#pcie +
base frequency1,100 MHz (1.1 GHz, 1,100,000 kHz) +
clock multiplier11 +
core count4 +
core nameGemini Lake +
core steppingB0 +
designerIntel +
device id0x3185 +
familyCeleron +
first announcedDecember 11, 2017 +
first launchedDecember 11, 2017 +
full page nameintel/celeron/n4100 +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Software Guard Extensions +, Smart Response Technology + and Identity Protection Technology +
has intel enhanced speedstep technologytrue +
has intel identity protection technology supporttrue +
has intel smart response technology supporttrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpuUHD Graphics 600 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units12 +
integrated gpu max frequency700 MHz (0.7 GHz, 700,000 KHz) +
integrated gpu max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB) +
isax86-64 +
isa familyx86 +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description6-way set associative +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldateDecember 11, 2017 +
main imageFile:gemini lake (front).png +
manufacturerIntel +
market segmentMobile +
max cpu count1 +
max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max memory bandwidth35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels2 +
microarchitectureGoldmont Plus +
model numberN4100 +
nameCeleron N4100 +
packageFCBGA-1090 +
part numberFH8068003067408 +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 107.00 (€ 96.30, £ 86.67, ¥ 11,056.31) +
s-specSR3S0 +
sdp4.8 W (4,800 mW, 0.00644 hp, 0.0048 kW) +
series4000 +
smp max ways1 +
supported memory typeDDR4-2400 +
tdp6 W (6,000 mW, 0.00805 hp, 0.006 kW) +
technologyCMOS +
thread count4 +
turbo frequency (1 core)2,400 MHz (2.4 GHz, 2,400,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +
x86/has software guard extensionstrue +