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By default, only the {{risc-v|integer base|core ISA}} must be implemented presenting great opportunity for area and energy optimization. However, additional functionality is sometimes desired. RISC-V comes with a series of standard extensions that enable additional functionality beyond the {{risc-v|integer base|core ISA}} such as [[floating point]] and operations and [[bit]] [[bit manipulation|manipulation]]. Extensions can be implemented and omitted as desired. Those extensions are:
 
By default, only the {{risc-v|integer base|core ISA}} must be implemented presenting great opportunity for area and energy optimization. However, additional functionality is sometimes desired. RISC-V comes with a series of standard extensions that enable additional functionality beyond the {{risc-v|integer base|core ISA}} such as [[floating point]] and operations and [[bit]] [[bit manipulation|manipulation]]. Extensions can be implemented and omitted as desired. Those extensions are:
  
−
* '''{{risc-v|A}}''' - Atomic instructions
+
{| class="wikitable"
−
* '''{{risc-v|B}}''' - Bit manipulation instructions
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|-
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* '''{{risc-v|C}}''' - Compressed instructions
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! Name !! Description !! Version !! Status !! Instruction Count
−
* '''{{risc-v|D}}''' - Double-precision floating-point instructions
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|-
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* '''{{risc-v|F}}''' - Single-precision floating-point instructions
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| RV32I || Base Integer Instruction Set - 32-bit || 2.1 || Frozen || 49
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* '''{{risc-v|G}}''' - General ({{risc-v|I}} + {{risc-v|M}} + {{risc-v|A}} + {{risc-v|F}} + {{risc-v|D}})
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|-
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* '''{{risc-v|I}}''' - Integer base instructions
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| RV32E || Base Integer Instruction Set (embedded) - 32-bit, 16 registers || 1.9 || Open || Same as RV32I
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* '''{{risc-v|J}}''' - Dynamically translated languages
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|-
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* '''{{risc-v|L}}''' - Decimal floating point instructions
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| RV64I || Base Integer Instruction Set - 64-bit || 2.0 || Frozen || 14
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* '''{{risc-v|M}}''' - Integer multiplication and division instructions
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|-
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* '''{{risc-v|N}}''' - User-level interrupt instructions
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| RV128I || Base Integer Instruction Set - 128-bit || 1.7 || Open || 14
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* '''{{risc-v|P}}''' - Packed-SIMD instructions
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|-
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* '''{{risc-v|Q}}''' - Quad-precision floating-point instructions
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! colspan=5 | Extension
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* '''{{risc-v|T}}''' - Transactional Memory instructions
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|-
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* '''{{risc-v|V}}''' - Vector operations instructions
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| M || Standard Extension for Integer Multiplication and Division || 2.0 || Frozen || 8
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|-
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| A || Standard Extension for Atomic Instructions || 2.0 || Frozen || 11
 +
|-
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| F || Standard Extension for Single-Precision Floating-Point || 2.0 || Frozen || 25
 +
|-
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| D || Standard Extension for Double-Precision Floating-Point || 2.0 || Frozen || 25
 +
|-
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| G || Shorthand for the base and above extensions || n/a || n/a || n/a
 +
|-
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| Q || Standard Extension for Quad-Precision Floating-Point || 2.0 || Frozen || 27
 +
|-
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| L || Standard Extension for Decimal Floating-Point || 0.0 || Open || Undefined Yet
 +
|-
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| C || Standard Extension for Compressed Instructions || 2.0 || Frozen || 36
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|-
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| B || Standard Extension for Bit Manipulation || 0.90 || Open || 42
 +
|-
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| J || Standard Extension for Dynamically Translated Languages || 0.0 || Open || Undefined Yet
 +
|-
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| T || Standard Extension for Transactional Memory || 0.0 || Open || Undefined Yet
 +
|-
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| P ||| Standard Extension for Packed-SIMD Instructions || 0.1 || Open || Undefined Yet
 +
|-
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| V || Standard Extension for Vector Operations || 1.0 || Frozen || 186
 +
|-
 +
| N || Standard Extension for User-Level Interrupts || 1.1 || Open || 3
 +
|-
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| H || Standard Extension for Hypervisor || 1.0 || Frozen || 2
 +
|-
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| S || Standard Extension for Supervisor-level Instructions || 1.12 || Open || 7
 +
|}
 +
 
 +
== Naming Convention ==
 +
RISC-V defines an exact order that must be used to define the RISC-V ISA subset:
 +
 
 +
: <code>RV [32, 64, 128]</code> <code>I, M, A, F, D, G, Q, L, C, B, J, T, P, V, N</code>
 +
 
 +
For example, <code>RV32IMAFDQC</code> is legal, whereas <code>RV32IMAFDCQ</code> is not.

Latest revision as of 08:18, 17 September 2024

RISC-V
Instruction Set Architecture
General
Base Variants(base)
Standard Extensions(all)
Topics

v · d · e

RISC-V has standardized a series of standard extensions beyond the integer base instructions which can be implemented or omitted as desired depending on the design goals (e.g. energy/area/performance/storage goals).

Overview[edit]

By default, only the core ISA must be implemented presenting great opportunity for area and energy optimization. However, additional functionality is sometimes desired. RISC-V comes with a series of standard extensions that enable additional functionality beyond the core ISA such as floating point and operations and bit manipulation. Extensions can be implemented and omitted as desired. Those extensions are:

Name Description Version Status Instruction Count
RV32I Base Integer Instruction Set - 32-bit 2.1 Frozen 49
RV32E Base Integer Instruction Set (embedded) - 32-bit, 16 registers 1.9 Open Same as RV32I
RV64I Base Integer Instruction Set - 64-bit 2.0 Frozen 14
RV128I Base Integer Instruction Set - 128-bit 1.7 Open 14
Extension
M Standard Extension for Integer Multiplication and Division 2.0 Frozen 8
A Standard Extension for Atomic Instructions 2.0 Frozen 11
F Standard Extension for Single-Precision Floating-Point 2.0 Frozen 25
D Standard Extension for Double-Precision Floating-Point 2.0 Frozen 25
G Shorthand for the base and above extensions n/a n/a n/a
Q Standard Extension for Quad-Precision Floating-Point 2.0 Frozen 27
L Standard Extension for Decimal Floating-Point 0.0 Open Undefined Yet
C Standard Extension for Compressed Instructions 2.0 Frozen 36
B Standard Extension for Bit Manipulation 0.90 Open 42
J Standard Extension for Dynamically Translated Languages 0.0 Open Undefined Yet
T Standard Extension for Transactional Memory 0.0 Open Undefined Yet
P Standard Extension for Packed-SIMD Instructions 0.1 Open Undefined Yet
V Standard Extension for Vector Operations 1.0 Frozen 186
N Standard Extension for User-Level Interrupts 1.1 Open 3
H Standard Extension for Hypervisor 1.0 Frozen 2
S Standard Extension for Supervisor-level Instructions 1.12 Open 7

Naming Convention[edit]

RISC-V defines an exact order that must be used to define the RISC-V ISA subset:

RV [32, 64, 128] I, M, A, F, D, G, Q, L, C, B, J, T, P, V, N

For example, RV32IMAFDQC is legal, whereas RV32IMAFDCQ is not.

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