Semiconductor & Computer Engineering
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Difference between revisions of "Template:risc-v isa main"
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* {{risc-v|History}} | * {{risc-v|History}} | ||
* {{risc-v|list of processor families|Families}} | * {{risc-v|list of processor families|Families}} | ||
| − | <div class="header">Base Variants</div> | + | <div class="header">Base Variants<small style="float: right;">({{risc-v|i|base}})</small></div> |
| − | * {{risc-v| | + | * {{risc-v|RV32}} |
| − | * {{risc-v| | + | * {{risc-v|RV64}} |
| − | * {{risc-v| | + | * {{risc-v|RV128}} |
<div class="header">Standard Extensions<small style="float: right;">({{risc-v|Standard Extensions|all}})</small></div> | <div class="header">Standard Extensions<small style="float: right;">({{risc-v|Standard Extensions|all}})</small></div> | ||
<div class="wiki-ul-col3"> | <div class="wiki-ul-col3"> | ||
| − | |||
* {{risc-v|A}} | * {{risc-v|A}} | ||
| + | * {{risc-v|B}} | ||
| + | * {{risc-v|C}} | ||
| + | * {{risc-v|D}} | ||
| + | * {{risc-v|E}} | ||
* {{risc-v|F}} | * {{risc-v|F}} | ||
| − | |||
* {{risc-v|G}} | * {{risc-v|G}} | ||
| + | * {{risc-v|I}} | ||
| + | * {{risc-v|J}} | ||
| + | * {{risc-v|L}} | ||
| + | * {{risc-v|M}} | ||
| + | * {{risc-v|N}} | ||
| + | * {{risc-v|P}} | ||
* {{risc-v|Q}} | * {{risc-v|Q}} | ||
| − | * {{risc-v| | + | * {{risc-v|T}} |
| + | * {{risc-v|V}} | ||
</div> | </div> | ||
<div class="header">Topics</div> | <div class="header">Topics</div> | ||
* {{risc-v|Foundation}} | * {{risc-v|Foundation}} | ||
| − | * {{risc-v| | + | * {{risc-v|Non-Standard Extensions}} |
* {{risc-v|Addressing Modes}} | * {{risc-v|Addressing Modes}} | ||
* {{risc-v|Registers}} | * {{risc-v|Registers}} | ||
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{{Navbar|Template:risc-v isa main|text=|mini=1|style=float:right;}} | {{Navbar|Template:risc-v isa main|text=|mini=1|style=float:right;}} | ||
</div> | </div> | ||
| + | [[category:risc-v]] | ||